RISC-V Software News

Spec Repository Activity

Notable Changes

• RISC-V: enable building 64-bit kernels with rust support (70a57b2472, Miguel Ojeda)
• bpf, riscv: Implement bpf_addr_space_cast instruction (21ab0b6d0c, Puranjay Mohan)
• riscv: hwprobe: fix invalid sign extension for RISCV_HWPROBE_EXT_ZVFHMIN (5ea6764d90, Clément Léger)
• riscv/cmpxchg: Implement xchg for variables of size 1 and 2 (and 3 more) (a8ed2b7a2c, Leonardo Bras)
• drivers/perf: riscv: Implement SBI PMU snapshot function (and 3 more) (a8625217a0, Atish Patra)
• riscv: dts: sophgo: add reserved memory node for CV1800B (and 5 more) (1eba0b61be, Inochi Amaoto)
• riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} (79d6e4eae9, Jisheng Zhang)
• riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI (808852fa3a, Lad Prabhakar)
• RISC-V: KVM: Implement kvm_arch_vcpu_ioctl_set_guest_debug() (edcbe90f12, Chao Du)
• RISCV: KVM: Introduce mp_state_lock to avoid lock inversion (2121cadec4, Yong-Xuan Wang)
• bpf, riscv: Implement PROBE_MEM32 pseudo instructions (633a6e01d1, Puranjay Mohan)
• riscv: Fix vector state restore in rt_sigreturn() (c27fa53b85, Björn Töpel)
• riscv: hwprobe: export Zihintpause ISA extension (63f93a3ca8, Clément Léger)
• riscv: config: enable ARCH_CANAAN in defconfig (cd899f85b1, Yangyu Chen)
• RISCV: KVM: Introduce vcpu->reset_cntx_lock (9752fed8f6, Yong-Xuan Wang)

Notable Changes

• lib: sbi: Add missing sscrind and sscfg extensions in sbi_hart_ext[] (and 3 more) (68bc031a76, Clément Léger)
• platform: generic: allwinner: Optimize current hart scratch access (f5375bc15e, Samuel Holland)
• lib: utils/timer: Optimize current hart scratch access (b94396c7dd, Samuel Holland)
• lib: sbi: Simplify wait_for_coldboot() implementation (beb0cd177f, Anup Patel)
• include: sbi: Support byteorder macros in assembly (5c9a73565f, Vivian Wang)
• sbi: sbi_domain_context: Check privilege spec version before accessing S-mode CSRs (29ecda9c20, Yu Chien Peter Lin)
• lib: utils: check correct value in fdt_node_offset_by_compatible (73344d4724, Heinrich Schuchardt)
• lib: sbi: Wakeup non-coldboot HARTs early in the coldboot path (7862c244bc, Anup Patel)
• Makefile: Respect manual changes to .config (268feab294, Samuel Holland)
• lib: sbi: sse_event_get() may return NULL (37e1544a86, Heinrich Schuchardt)
• Makefile: Remove unnecessary dependencies (a7c5c2cbd2, Samuel Holland)
• firmware: remove copy-base relocation (76d7e9b8ee, Xiang W)
• firmware: remove FW_TEXT_START (d4d2582eef, Xiang W)

Notable Changes

• hw, target: Add ResetType argument to hold and exit phase methods (ad80e36744, Peter Maydell)
• hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER device (259181d29f, Thomas Huth)
• exec: Declare CPUBreakpoint/CPUWatchpoint type in 'breakpoint.h' header (6ce1c9d085, Philippe Mathieu-Daudé)
• target/riscv/kvm: remove sneaky strerrorname_np() instance (e442635317, Daniel Henrique Barboza)
• target: Define TCG_GUEST_DEFAULT_MO in 'cpu-param.h' (e92dd33224, Philippe Mathieu-Daudé)
• target/riscv: Use insn_start from DisasContextBase (401aa608d8, Richard Henderson)
• hw/riscv/virt: Replace sprintf by g_strdup_printf (b8ff846ec8, Philippe Mathieu-Daudé)
• KVM: remove kvm_arch_cpu_check_are_resettable (a99c0c66eb, Paolo Bonzini)

Notable Changes

• [LV, VP]VP intrinsics support for the Loop Vectorizer + adding new tail-folding mode using EVL. (#76172) (413a66f339, Alexey Bataev)
• [RISCV] Only support SPLAT_VECTOR for Zvfhmin when also enable the scalar extension of half fp (#88275) (fd50151180, Jianjian Guan)
• [RISCV] Use vwadd.vx for splat vector with extension (#87249) (469caa31e7, Chia)
• [LegalizeTypes][RISCV] Support scalable vectors in SplitVecRes_BITCAST/SplitVecOp_BITCAST. (#88590) (342aa3eb23, Craig Topper)
• Reapply "[RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295)" (af82d01fbb, Luke Lau)
• Revert "[RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295)" (fc13353e10, Luke Lau)
• [RISCV] Support codegen of vfmv.v.f for bfloat vector with both Zvfbfmin and Zfbfmin (#87318) (bc8726b16b, Jianjian Guan)
• [RISCV] Separate doLocalPostpass into new pass and move to post vector regalloc (#88295) (603ba4c596, Luke Lau)
• [RISCV] Add test for miscompile of vector.interleave when odd vector is literal poison. (8c1dc5dd58, Craig Topper)
• Reapply "[RISCV] Implement RISCVISD::SHL_ADD and move patterns into combine (#89263)" (03760ad09d, Philip Reames)
• Revert "[RISCV] Implement RISCVISD::SHL_ADD and move patterns into combine (#89263)" (dc3f94384d, Philip Reames)
• [RISCV] Implement RISCVISD::SHL_ADD and move patterns into combine (#89263) (5a7c80ca58, Philip Reames)
• [RISCV] Add CFI information for vector callee-saved registers (#86811) (c81e5faa6f, Brandon Wu)
• [RISCV] Optimize undef Even vector in getWideningInterleave. (#88221) (323d3ab257, Craig Topper)
• [RISCV] Add extension information to RISCVFeatures.td. NFC (#89326) (a6c028299c, Craig Topper)

Notable Changes

• login: Check default sizes of structs utmp, utmpx, lastlog (4d4da5aab9, Florian Weimer)

Notable Changes

• RISC-V: Support Zcmp push/pop instructions. (9132c8152b, Jiawei)
• PR 30569, always call elf_backend_size_dynamic_sections (af969b14ae, Alan Modra)

Notable Changes

• sim: riscv: Fix confusion with c.jal vs. c.addiw (and 2 more) (d8e753b791, Bernd Edlinger)
• gdb: move store/extract integer functions to extract-store-integer.{c,h} (ec45252592, Simon Marchi)
• Remove excess whitespace from doc strings of some commands (6a2dbb742d, Eli Zaretskii)
• gdb: remove gdbcmd.h (5b9707eb87, Simon Marchi)

Notable Changes

• riscv: support extension probing using riscv, isa-extensions (f39b1b77d8, Conor Dooley)
• riscv: cpu: cv1800b: Add support for cv1800b SoC (ae800aa79a, Kongyang Liu)
• Revert "Merge patch series "pxe: Allow extlinux booting without CMDLINE enabled"" (cdd20e3f66, Tom Rini)
• riscv: add backtrace support (e4f69492ad, Ben Dooks)
• riscv: dts: sophgo: Add clk node and sdhci node (b0a09b21e9, Kongyang Liu)
• board: starfive: support Milk-V Mars board (92db23f766, Heinrich Schuchardt)
• riscv: cache: Implement dcache for cv1800b (c21dfcb556, Kongyang Liu)
• riscv: don't read riscv, isa in the riscv cpu's get_desc() (b90edde701, Conor Dooley)
• treewide: Make arch-specific bootm code depend on BOOTM (6be5ec948b, Simon Glass)
• eeprom: starfive: function get_product_id_from_eeprom() (90e9dcd709, Heinrich Schuchardt)
• common: Convert *.c/h from UTF-8 to ASCII enconfing (81f3a665ab, Michal Simek)
• riscv: do not set default fdt for VisionFive 2 (0f6310c7ff, Heinrich Schuchardt)
• riscv: Move virtio scan to board_late_init() (c532ddded9, Łukasz Stelmach)
• riscv: starfive: avoid including common.h (3fe5a37f32, Heinrich Schuchardt)
• riscv: set fdtfile on Milk-V Mars (0a8b83fb30, Heinrich Schuchardt)

Notable Changes

• flash/nor/eneispif: support ENE KB1200 ispi flash (dd17582722, Steven Chang)