In May 2024, the RISC-V ecosystem saw 252 commits across 11 projects. The most active projects were LLVM (RISC-V) (127), Linux Kernel (RISC-V) (47), OpenSBI (30). Extension support continued to broaden, with work on Smstateen, Zaamo, Zalrsc, Zba, Zicsr. Most-discussed mailing list thread: "miscellaneous about sbi_dtbr" (OpenSBI, 11 replies).
RISC-V International
The spec repos saw 81 commits this month, led by ISA Manual with 57 commits.
Spec Repository Activity
Repository
Commits
Contributors
ISA Manual
57
15
Debug Spec
12
3
Profiles
5
3
SBI Spec
4
3
ELF psABI
3
3
Linux Kernel (RISC-V)
47
Commits
23
Contributors
754
Lines Added
381
Lines Removed
A productive month for Linux Kernel (RISC-V) with 47 commits from 23 contributors. Leading the charge was Andy Chiu with 6 commits. New feature work included 8 commits: "riscv: hwprobe: add zve Vector subextensions into hwprobe interface"; "riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection". Bug fixes accounted for 7 commits (14%). Vector extension support moved forward with 5 commits. Work on Zba accounted for 4 commits.
8 New features & support7 Bug fixes5 Vector extension (RVV)4 ISA extensions4 Device tree / platform support2 Performance optimisations1 Interrupt controllers (AIA/APLIC/PLIC)1 Cleanup & refactoring
Notable Changes
riscv: hwprobe: add zve Vector subextensions into hwprobe interface (de8f8282a9, Andy Chiu)
riscv: vector: add a comment when calling riscv_setup_vsize() (77afe3e514, Andy Chiu)
riscv: add support for kernel-mode FPU (and 2 more) (77acc6b55a, Samuel Holland)
riscv: cpufeature: call match_isa_ext() for single-letter extensions (98a5700dfa, Andy Chiu)
riscv: cpufeature: add zve32[xf] and zve64[xfd] isa detection (1e7483542b, Andy Chiu)
riscv: enable HAVE_ARCH_HUGE_VMAP for XIP kernel (and 2 more) (7bed516174, Nam Cao)
A steady month for OpenSBI with 30 commits from 11 contributors. Clément Léger was the most active contributor with 8 commits. New feature work included 9 commits: "lib: utils/irqchip: Add sanity checks in imsic_get_data() and imsic_get_target_file()"; "platform: generic: thead: add Sophgo CV18XX/SG200X series". Bug fixes accounted for 4 commits (13%). The interrupt subsystem got 2 patches of attention this month. On the mailing list, "[PATCH v4] firmware: remove FW_TEXT_START" drew 10 replies.
9 New features & support4 Bug fixes2 Interrupt controllers (AIA/APLIC/PLIC)2 Cleanup & refactoring
LLVM (RISC-V) saw heavy activity with 127 commits from 31 contributors. +27,038/-17,807 lines changed — a big diff. Top contributor: Craig Topper with 39 commits. Code generation improvements dominated with 38 commits. New feature work included 35 commits: "[DAGCombiner][VP] Add DAGCombine for VP_MUL (#80105)"; "[RISCV] Support (truncate (smin (smax X, C1), C2)) for vnclipu in combineTruncToVnclip. (#93756)". The vector extension (RVV) saw 29 commits of continued development.
39 Cleanup & refactoring38 Compiler backend / code generation35 New features & support29 Vector extension (RVV)10 ISA extensions5 Bug fixes1 Security & memory safety fixes
Notable Changes
[RISCV] Inogre CallingConv::RISCV_VectorCall in getCalleeSavedRegs if V/Zve is not enabled. (435771228c, Craig Topper)
[RISCV] Refactor combineTruncToVnclipu to prepare for adding signed vnclip support. NFC (424f82c204, Craig Topper)
[GISel] Add narrowScalar/widenScalar support for `G_CONSTANT_FOLD_BARRIER` (#93031) (821bcba00d, Yingwei Zheng)
[TableGen][RISCV] Add initial support for marking profiles as experimental (#91993) (e5a277b167, Alex Bradbury)
[GISel][RISCV] Add irtranslator/legalizer/selector support for G_FREEZE. (#92744) (76748119bf, Yingwei Zheng)
[RISCV] Gate unratified profiles behind -menable-experimental-extensions (#92167) (891d687137, Alex Bradbury)
[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch (#92195) (4ab2ac22d0, Patrick O'Neill)
[RISCV] Teach .option arch to support experimental extensions. (#89727) (d70267fbae, Yeting Kuo)
[RISCV] Support interleaved accesses for scalable vector. (#90583) (3f1fef3699, Mel Chen)
[RISCV] Add Sched classes for vector crypto instructions (#90068) (56b8bd7744, Michael Maitland)
[RISCV][llvm-mca] Add vector crypto llvm-mca tests for P600 (4821882cdf, Michael Maitland)
[RISCV] Codegen support for XCVbi extension (#89719) (f4d2f7a3b7, Liao Chunyu)
[RISCV] Pass subvector type to isLegalInterleavedAccessType in getInterleavedMemoryOpCost. (#91825) (487b43cdc9, Craig Topper)
[RISCV] Add codegen support for Zvfbfmin (#87911) (37fcb323f6, Jianjian Guan)
[RISCV] Add isel special case for (and (shl X, c2), c1) -> (slli_uw (srli x, c3-c2), c3). (#91638) (dfff57e751, Craig Topper)
Top Contributors
Author
Commits
Craig Topper
39
Luke Lau
27
Yingwei Zheng
11
Michael Maitland
6
Yeting Kuo
5
Min-Yih Hsu
4
Philip Reames
4
Alex Bradbury
4
Jianjian Guan
2
Sergei Barannikov
2
glibc (RISC-V)
2
Commits
2
Contributors
16
Lines Added
1
Lines Removed
Minimal activity in glibc (RISC-V): 2 commits from 2 contributors.
1 New features & support
Notable Changes
Implement C23 log2p1 (79c52daf47, Joseph Myers)
Remove the clone3 symbol from libc.a [BZ #31770] (437c94e04b, H.J. Lu)
Top Contributors
Author
Commits
H.J. Lu
1
Joseph Myers
1
Binutils (RISC-V)
5
Commits
3
Contributors
137
Lines Added
121
Lines Removed
Not the busiest month for Binutils (RISC-V): 5 commits from 3 contributors. Most of the work came from Nelson Chu (3 of 5 commits, 60%). Extension support saw 1 commit covering Zaamo, Zalrsc.
1 ISA extensions1 New features & support
Notable Changes
RISC-V: PR31733, Change initial CFI operation from DW_CFA_def_cfa_register to DW_CFA_def_cfa (3ce12d6d4a, Sung-hun Kim)
RISC-V: Fixed overwritten IRELATIVE relocs in the .rel.iplt for data reloc. (and 2 more) (e8c2682572, Nelson Chu)
RISC-V: Search for mapping symbols from the last one found (7a7ec56c81, Joseph Faulls)
GDB (RISC-V) had exactly one commit this month. Bug fixes dominated: 1/1 commits (100%). A month focused on getting things right.
1 Bug fixes
Notable Changes
sim: riscv: Fix build issue due to recent binutils commit (b75187cd94, Bernd Edlinger)
Top Contributors
Author
Commits
Bernd Edlinger
1
U-Boot (RISC-V)
22
Commits
7
Contributors
684
Lines Added
56
Lines Removed
U-Boot (RISC-V) saw moderate activity with 22 commits from 7 contributors. Top contributor: Tom Rini with 6 commits. New feature work included 10 commits: "board: starfive: support Pine64 Star64 board"; "board: starfive: support Pine64 Star64 board".
10 New features & support4 Device tree / platform support2 Bug fixes2 Cleanup & refactoring1 ISA extensions
Notable Changes
cmd: sbi: add Supervisor Software Events extension (c57c187bd4, Heinrich Schuchardt)
board: add support for Milk-V Mars CM (de3229599d, Heinrich Schuchardt)
board: sipeed: Remove and add needed includes (dbfdce274f, Tom Rini)
board: thead: Remove and add needed includes (31534d8ad5, Tom Rini)
starfive: add mac vendor sub-command (fcaf019c4e, Heinrich Schuchardt)
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" (d678a59d2d, Tom Rini)
Restore patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet" (03de305ec4, Tom Rini)
board: starfive: Rename spl_soc_init() to spl_dram_init() (19b762cf83, Lukas Funke)
global: Make include (6a7185887b, Tom Rini)
Top Contributors
Author
Commits
Tom Rini
6
Heinrich Schuchardt
6
Leo Yu-Chi Liang
3
H Bell
2
Lukas Funke
2
Kongyang Liu
2
Yu Chien Peter Lin
1
OpenOCD (RISC-V)
3
Commits
2
Contributors
15
Lines Added
4
Lines Removed
OpenOCD (RISC-V) was quiet this month with 3 commits from 2 contributors. Most of the work came from R. Diez (2 of 3 commits, 66%). Stabilisation was the theme, with fixes accounting for 2/3 commits (66%).
2 Bug fixes1 New features & support
Notable Changes
target/target: Add 'debug_reason' to current target (8667a72653, Marc Schink)