RISC-V Software News

Spec Repository Activity

Notable Changes

• riscv, bpf: Introduce shift add helper with Zba optimization (96a27ee76f, Xiao Wang)
• riscv: add ISA extension parsing for Zcmop (and 3 more) (164d644059, Clément Léger)
• riscv: mm: Add support for ZONE_DEVICE (and 7 more) (216e04bf1e, Björn Töpel)
• riscv: dmi: Add SMBIOS/DMI support (d6ecd18893, Haibo Xu)
• riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uarts (4ed81d9dd7, Hal Feng)
• function_graph: Everyone uses HAVE_FUNCTION_GRAPH_RET_ADDR_PTR, remove it (5f7fb89a11, Steven Rostedt (Google))
• riscv: dts: microchip: add an initial devicetree for the BeagleV Fire (3f41368fbf, Conor Dooley)
• RISC-V: KVM: Allow Zcmop extension for Guest/VM (and 2 more) (29cf9b803e, Clément Léger)
• riscv: hwprobe: export Zcmop ISA extension (and 2 more) (fc078ea317, Clément Léger)
• RISCV: KVM: add tracepoints for entry and exit events (91195a90f1, Shenlin Liang)
• riscv: dts: starfive: add Star64 board devicetree (2606bf583b, Henry Bell)
• riscv: defconfig: Enable StarFive JH7110 drivers (d8a7d89abb, Hal Feng)
• RISC-V: fix vector insn load/store width mask (04a2aef59c, Jesse Taube)
• riscv: dts: thead: th1520: Add PMU event node (c61fea676b, Inochi Amaoto)
• riscv: Enable memory hotplugging for RISC-V (f8c2a24055, Björn Töpel)

Notable Changes

• lib: sbi: Add support for Svade and Svadu extensions (53844c98d0, Yong-Xuan Wang)
• platform: generic: andes: Add support for RV32 to set up PMA (52dcf351cd, Ben Zong-You Xie)
• lib: utils/irqchip: Skip initialize irqchip when dt is not enabled (b1c7c750f7, Xiang W)
• lib: utils/serial: Skip initialize serial when dt is not enabled (179e00a320, Xiang W)
• lib: utils/timer: Skip initialize timer when dt is not enabled (5e3ad7d577, Xiang W)
• lib: utils/ipi: Skip initialize ipi when dt is not enabled (c5be0e1ed1, Xiang W)
• lib: sbi: check incoming dbtr shmem address (23b7badeee, Sergey Matyukevich)
• lib: sbi: fwft: return SBI_EINVAL rather than SBI_ERR_INVALID_PARAM (and 5 more) (caae2f7d45, Clément Léger)
• lib: utils/reset: Try initializing all reset devices in dt (and 2 more) (62e178a0a7, Xiang W)
• sbi: sbi_domain_context: Fix trap context for domain context switching (3a94a32580, Yu Chien Peter Lin)
• lib: utils/serial: Fix fdt_serial to match more dt nodes (86bbe6c52f, Xiang W)
• platform: generic: andes: Refine Andes PMA related code (f09f16430a, Ben Zong-You Xie)
• lib: utils/fdt: Fix DT property for APLIC delegation (df3db6a901, Anup Patel)
• lib: serial: fix RX path in litex-uart (7830e98785, Gabriel Somlo)
• docs: Fix wrong filename (0e45b63471, Jacob Lin)

Notable Changes

• target/riscv/kvm: add software breakpoints support (80b605056d, Chao Du)
• target/riscv: rvv: Remove redudant SEW checking for vector fp narrow/widen instructions (and 3 more) (93cb52b7a3, Max Chou)
• hw/riscv/boot.c: Support 64-bit address for initrd (0390039950, Cheng Yang)
• target/riscv: Remove extension auto-update check statements (and 5 more) (cb5b50d91d, Frank Chang)
• target/riscv: Relax vector register check in RISCV gdbstub (and 2 more) (4a90991234, Jason Chien)
• riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature() (583edc4efb, Daniel Henrique Barboza)
• target/riscv: rvzicbo: Fixup CBO extension register calculation (c5eb8d6336, Alistair Francis)
• target/riscv: Implement dynamic establishment of custom decoder (8c8a7cd647, Huang Tao)
• hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible' (8fb0bb5e8a, Daniel Henrique Barboza)
• hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible' (362b31fc35, Daniel Henrique Barboza)
• target/riscv: Remove experimental prefix from "B" extension (73ef14b127, Rob Bradford)
• target/riscv/kvm: implement SBI debug console (DBCN) calls (a6b53378f5, Daniel Henrique Barboza)
• target/riscv: Support the version for ss1p13 (and 4 more) (3adf4def19, Fea.Wang)
• disas/riscv: Decode all of the pmpcfg and pmpaddr CSRs (915758c537, Alistair Francis)
• target/riscv/cpu.c: fix Zvkb extension config (ff33b7a969, Yangyu Chen)

Notable Changes

• [RISCV] Unify all the code that adds unaligned-scalar/vector-mem to Features vector. (#94660) (2d65097b4f, Craig Topper)
• Reland "[RISCV] Support select/merge like ops for bf16 vectors when have Zvfbfmin" (#94565)" (be18daad06, Jianjian GUAN)
• Revert "[RISCV] Support select/merge like ops for bf16 vectors when have Zvfbfmin" (#94565) (8c452d0cc5, Mehdi Amini)
• [clang] Reland Add tanf16 builtin and support for tan constrained intrinsic (#94559) (189d471191, Farzon Lotfi)
• [RISCV] Support select/merge like ops for bf16 vectors when have Zvfbfmin (#91936) (d5ab38f69c, Jianjian Guan)
• [RISCV] Make the vsll->vadd intrinsic pattern support tail undisturbed intrinsics. (a3d9ca9297, Craig Topper)
• [RISCV][GISel] Add calling convention support for half (#94110) (643e4718af, Yingwei Zheng)
• [RISCV][NFC] Add UnsupportedSched multiclasses (#95948) (1a364b4eef, Anton Sidorenko)
• [CodeGen] Support vectors across all backends (#95518) (6355fb45a5, Farzon Lotfi)
• [RISCV] Codegen support for XCVmem extension (#76916) (2afea72968, Liao Chunyu)
• [RISCV] Add Smcsrind and Sscsrind extension (#93952) (2fe72385a4, Monad)
• [RISCV] Add smcdeleg and ssccfg extensions (#95163) (307d91ee62, Monad)
• Recommit "[RISCV] Use vadd.vi for tail undisturbe vsub intrinsic with small immediate." (baa6609fad, Craig Topper)
• [CodeGen][NewPM] Split `MachineDominatorTree` into a concrete analysis result (#94571) (837dc542b1, paperchalice)
• Revert "[RISCV] Use vadd.vi for tail undisturbe vsub intrinsic with small immediate." (16aef9ec52, Craig Topper)

Notable Changes

• Implement C23 exp2m1, exp10m1 (7ec903e028, Joseph Myers)
• Implement C23 log10p1 (55eb99e9a9, Joseph Myers)
• Implement C23 logp1 (bb014f50c4, Joseph Myers)
• Convert to autoconf 2.72 (vanilla release, no distribution patches) (98ffc1bfeb, Andreas K. Hüttel)
• RISC-V: Execute a PAUSE hint in spin loops (81c7f6193c, Christoph Müllner)
• RISC-V: Update ulps (9f2bf0e23a, Julian Zhu)

Notable Changes

• RISC-V: Add support for XCVmem extension in CV32E40P (and 2 more) (29de80758f, Mary Bennett)
• RISC-V: Add support for Zvfbfwma extension (and 2 more) (0b4595be3f, Xiao Zeng)
• opcodes/riscv: add styling support to print_reg_list (47277edc32, Andrew Burgess)
• RISC-V: Add Zabha extension CAS instructions. (805df5e4a8, Jiawei)
• RISC-V: Support S[sm]csrind extension csrs. (b7641ae1af, Jiawei)
• RISC-V: Add SiFive cease extension v1.0 (7003edc383, Hau Hsu)
• RISC-V: Support Zacas extension. (88729e9616, Gianluca Guida)
• RISC-V: Remove implicit enablement of Zvknha from Zvkn. (da16a23481, Feng Wang)
• opcodes/riscv: prevent future use of disassemble_info::fprintf_func (5ccd31931e, Andrew Burgess)
• RISC-V: Shrink the riscv_implicit_subsets table. (and 2 more) (685dcd295a, Nelson Chu)

Notable Changes

• flash/nor/nrf5: add basic nRF53 and nRF91 support (d94daf776c, Tomas Vanek)
• target/riscv: support for smp group manipulation (d382c95d57, Parshintsev Anatoly)
• doc: Minimally describe the BSCAN tunnel interface. (2f8bb252ff, Tim Newsome)
• pld/intel: remove idcodes from intel.c (9bc7a381b2, Daniel Anselmi)
• pld: small documentation fixes. (bf4be566a7, Daniel Anselmi)

Notable Changes

• Drop the -static Fortran flag from generic builds as it breaks OpenMP (df87aeb5a2, Martin Kroeker)
• Handle INF and NAN in inputs (c1019d5832, Martin Kroeker)

Notable Changes

• dt-bindings: riscv: add Zcmop ISA extension description (and 2 more) (700556a73b, Clément Léger)
• dt-bindings: riscv: cpus: add ref to interrupt-controller (1f6e218859, Kanak Shilledar)
• dt-bindings: riscv: starfive: add Star64 board compatible (c249e17c37, Henry Bell)
• dt-bindings: riscv: microchip: document beaglev-fire (76ed031dc7, Conor Dooley)