RISC-V Software News - September 2024

Linux Kernel (RISC-V) (56 commits)
OpenSBI (30 commits)
QEMU (RISC-V) (5 commits)
LLVM (RISC-V) (184 commits)
glibc (RISC-V) (1 commits)
Binutils (RISC-V) (4 commits)
U-Boot (RISC-V) (14 commits)
Rust (RISC-V) (5 commits)
OpenOCD (RISC-V) (3 commits)
Linux Kernel Docs & DT (RISC-V) (2 commits)

The Big Picture

September 2024 saw 304 commits land across 10 tracked projects. LLVM (RISC-V) led with 184 commits (60%). Also active: Linux Kernel (RISC-V) (56), OpenSBI (30), U-Boot (RISC-V) (14). Extension support continued to broaden, with work on Zacas, Zdinx, Zfhmin, Zfinx, Zhinx, Zhinxmin, Zicsr, Zvfh. Samuel Holland authored 70% of OpenSBI commits this month. Most-discussed mailing list thread: "lib: sbi: fwft: factorize menvcfg read/write (3-patch series)" (OpenSBI, 8 replies).

RISC-V International

The spec repos saw 43 commits this month, led by ISA Manual with 23 commits.

Spec Repository Activity

Repository	Commits	Contributors
ISA Manual	23	12
SBI Spec	14	6
ELF psABI	3	3
Debug Spec	2	2
Profiles	1	1

Linux Kernel (RISC-V)

Commits

Contributors

844

Lines Added

270

Lines Removed

A productive month for Linux Kernel (RISC-V) with 56 commits from 27 contributors. Top contributor: Nam Cao with 8 commits. New feature work included 23 commits: "perf/riscv-sbi: Add platform specific firmware event handling"; "riscv: Enable bitops instrumentation". Device tree and platform support saw 11 commits. Bug fixes accounted for 5 commits (8%). 4 commits targeted performance improvements.

23 New features & support 11 Device tree / platform support 5 Bug fixes 4 Performance optimisations 3 Cleanup & refactoring 2 Interrupt controllers (AIA/APLIC/PLIC) 1 KVM / Virtualisation 1 Vector extension (RVV) 1 ISA extensions

Notable Changes

RISC-V: Implement kgdb_roundup_cpus() to enable future NMI Roundup (983f121499, Jinjie Ruan)
riscv: defconfig: Enable pinctrl support for CV18XX Series SoC (72160ec6cb, Inochi Amaoto)
riscv: stacktrace: Add USER_STACKTRACE support (1a74833182, Jinjie Ruan)
riscv: Stop emitting preventive sfence.vma for new userspace mappings with Svvptc (and 4 more) (7a21b2e370, Alexandre Ghiti)
irqchip/sifive-plic: Add ACPI support (206dd13a10, Sunil V L)
riscv: boot: add Image.xz support (ab4ce9831a, Lasse Collin)
RISC-V: configs: enable I2C_DESIGNWARE_CORE with I2C_DESIGNWARE_PLATFORM (0175b1d3c6, Heikki Krogerus)
riscv: dts: sophgo: Add mcu device for Milk-V Pioneer (and 4 more) (585dcb21cc, Inochi Amaoto)
perf/riscv-sbi: Add platform specific firmware event handling (f0c9363db2, Mayuresh Chitale)
riscv: sophgo: dts: add gpio controllers for SG2042 SoC (a508d794f8, Chen Wang)
RISC-V: Don't have MAX_PHYSMEM_BITS exceed phys_addr_t (ad380f6a0a, Palmer Dabbelt)
riscv: Omit optimized string routines when using KASAN (58ff537109, Samuel Holland)
riscv: cacheinfo: Add back init_cache_level() function (1845d381f2, Steffen Persvold)
riscv: sophgo: dts: add mmc controllers for SG2042 SoC (014b839f79, Chen Wang)
riscv: defconfig: Disable RZ/Five peripheral support (e36ddf3226, Geert Uytterhoeven)

Top Contributors

Author	Commits
Nam Cao	8
Alexandre Ghiti	6
Inochi Amaoto	6
Jinjie Ruan	5
Charlie Jenkins	4
Jisheng Zhang	4
Samuel Holland	2
Chen Wang	2
Mayuresh Chitale	1
Palmer Dabbelt	1

Notable Discussions

Re: [PATCH RFC v2 2/3] riscv: Add Svukte extension support — Deepak Gupta
Re: [PATCH RFC v2 1/3] dt-bindings: riscv: Add Svukte entry — Deepak Gupta

Mailing List Activity

Re: [PATCH v2 03/13] KVM: selftests: Fudge around an apparent gcc bug in arm64's PMU test — Sean Christopherson
Re: [PATCH v2 03/13] KVM: selftests: Fudge around an apparent gcc bug in arm64's PMU test — Sean Christopherson
Re: [PATCH] Documentation: riscv: Fix typo MIMPLID -> MIMPID — Nam Cao
[PATCH] riscv: traps: make insn fetch common in unknown instruction — Ben Dooks
pinctrl: Add T-Head TH1520 SoC pin controllers (8-patch series) — Drew Fustini

OpenSBI

Commits

Contributors

414

Lines Added

253

Lines Removed

OpenSBI saw moderate activity with 30 commits from 7 contributors. Samuel Holland dominated with 21/30 commits (70%). Bug fixes accounted for 6 commits (20%). AIA and interrupt controller work accounted for 2 patches.

6 Bug fixes 5 New features & support 2 ISA extensions 2 Interrupt controllers (AIA/APLIC/PLIC) 1 Cleanup & refactoring 1 Device tree / platform support

Notable Changes

include: adding support for Zicfilp / Zicfiss encodings (6758a756c4, Deepak Gupta)
lib: sbi: fwft: implement landing pad and shadow stack fwft interface (and 2 more) (7179e36ce7, Deepak Gupta)
include: sbi_bitops: add ULL version for BIT and GENMASK (570b9ae89a, Zong Li)
lib: sbi: fix missing high 32bits when sbi_cppc_write on rv32 (2ffa0a153d, Xiang W)
include: sbi: Don't unconditionally define '__always_inline' (7b3de48cd5, Elyes Haouas)
lib: sbi_ecall_legacy: Use SBI v0.2 encoding for "all harts" (633e7cbd50, Samuel Holland)
include: sbi: Store the hart index in struct sbi_scratch (9d7a983060, Samuel Holland)
lib: sbi: Remove unused hartid parameters (and 10 more) (9155024972, Samuel Holland)
lib: utils/ipi: Fix hartid wrongly used as hart index (cae230c935, Samuel Holland)
lib: utils/irqchip: Look up IMSIC data by hart index (7f5fa9f9a4, Samuel Holland)
firmware: Simplify FDT header endianness conversion (7c40909159, Samuel Holland)
Makefile: Make .carray.c files depend on carray.sh (bfa9f9aee7, Samuel Holland)
lib: sbi_sse: Cache the event's target hart index (d73a4c741c, Samuel Holland)
firmware: fw_base.S: fix multi-core boot bug. (3e141a6950, dong.yang)
lib: sbi_domain_context: Fix file permissions (040fcf49ab, Samuel Holland)

Top Contributors

Author	Commits
Samuel Holland	21
Deepak Gupta	4
Xiang W	1
dong.yang	1
Elyes Haouas	1
Zong Li	1
Atish Patra	1

Notable Discussions

lib: sbi: fwft: factorize menvcfg read/write (3-patch series) 8 replies — Samuel Holland
[PATCH] lib: sbi: Add support to mask/unmask SSE events 3 replies — Samuel Holland
Makefile: enable --gc-sections 3 replies — Bin Meng

Mailing List Activity

lib: sbi: add Ssdbltrp ISA extension support 2 — Clément Léger
include: adding support for Zicfilp / Zicfiss encodings (2-patch series) 2 — Deepak Gupta
lib: sbi: fwft: implement landing pad and shadow stack fwft interface 1 — Clément Léger
lib: sbi: add zicfilp/zicfiss and elp cfi state reflect back in status 1 — Samuel Holland
lib: sbi: send a double trap SSE event to supervisor 1 — Samuel Holland
platform: ensure enough heap size with debug triggers extension 1 — Inochi Amaoto
platform: introduce DT-based configurable heap size 1 — Xiang W
Prepare memregion handling for future isolation primitives 1 — Gregor Haas
[PATCH] Makefile: Make .carray.c files depend on carray.sh — Ben Dooks

QEMU (RISC-V)

Commits

Contributors

481

Lines Added

711

Lines Removed

A quieter month for QEMU (RISC-V), with 5 commits from 3 contributors. A net deletion month (+481/-711) — always satisfying.

1 Cleanup & refactoring

Notable Changes

license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later (97d348cc15, Philippe Mathieu-Daudé)
target/riscv: remove break after g_assert_not_reached() (e67d261240, Pierrick Bouvier)
target/riscv: Remove the deprecated 'any' CPU type (d83234d347, Philippe Mathieu-Daudé)
linux-user: update syscall_nr.h to Linux v6.10 (3f89ff9b60, Laurent Vivier)
linux-user,riscv: move to syscalltbl file (5281a1975c, Laurent Vivier)

Top Contributors

Author	Commits
Laurent Vivier	2
Philippe Mathieu-Daudé	2
Pierrick Bouvier	1

Mailing List Activity

[PATCH] target/riscv: Set vtype.vill on CPU reset — Rob Bradford
[PATCH] hw/riscv/spike: Replace tswap64() by ldq_endian_p() — Philippe Mathieu-Daudé
Re: [PATCH v3 02/14] hw/display/apple-gfx: Adds PCI implementation — BALATON Zoltan
hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support (12-patch series) — Phil Dennis-Jordan

LLVM (RISC-V)

184

Commits

Contributors

71916

Lines Added

31164

Lines Removed

Plenty of action in LLVM (RISC-V) this month: 184 commits from 29 contributors. +71,916/-31,164 lines changed — a big diff. Leading the charge was Craig Topper with 83 commits. New feature work included 43 commits: "[RISCV] Add correct MachinePointerInfo when putting arguments on the stack. (#110140)"; "[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)". Code generation improvements dominated with 38 commits. Work on Zacas, Zdinx, Zfhmin, Zfinx, Zhinx, Zhinxmin accounted for 34 commits.

53 Cleanup & refactoring 43 New features & support 38 Compiler backend / code generation 34 ISA extensions 20 Bug fixes 9 Vector extension (RVV) 1 Performance optimisations

Notable Changes

[RISCV] Support fastcc passing scalable vectors indirectly with no free GPRs. (#107623) (d5ef3f8c94, Craig Topper)
[RISCV] Support fixed vector VP_LOAD/STORE for bf16 and f16 without Zvfh. (#107297) (c82a5496c8, Craig Topper)
[IRTranslator][RISCV] Support scalable vector zeroinitializer. (#108666) (367c145e5f, Craig Topper)
[RISCV] Add fixed length vector patterns for vfwmaccbf16.vv (#108204) (480f07ff6c, Luke Lau)
[RISCV] Add explicit XLenVT cast to vector load/store patterns. (9d3a57633e, Craig Topper)
[LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32 when we don't have Zvfh. (#106652) (3e798476de, Craig Topper)
[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637) (ff0f2011e4, Craig Topper)
[RISCV] Add fastcc support for bf16 with Zfbfmin. (748ae69b5d, Craig Topper)
[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298) (b2e8b8fac0, Craig Topper)
[Clang][RISCV] Recognize unsupport target feature by supporting isValidFeatureName (#106495) (022b3c27e2, Piyou Chen)
[RISCV] Use CCValAssign::getCustomReg for fixed vector arguments/returns with RVV. (#108470) (ee4582f9c8, Craig Topper)
[RISCV] Remove unnecessary vand.vi from vXi1 and nvXvi1 VECTOR_REVERSE codegen. (#109071) (8e4909aa19, Craig Topper)
[LegalizeVectorOps][RISCV] Don't scalarize FNEG in ExpandFNEG if FSUB is marked Promote. (d21a43579e, Craig Topper)
[LegalizeTypes][RISCV] Use SPLAT_VECTOR_PARTS to legalize splat BUILD_VECTOR (#107290) (c28b1a19aa, Craig Topper)
[RISCV] Add correct MachinePointerInfo when putting arguments on the stack. (#110140) (8ed18eded9, Craig Topper)

Top Contributors

Author	Commits
Craig Topper	83
Luke Lau	35
Philip Reames	16
Fangrui Song	5
Elvis Wang	5
Alex Bradbury	4
Simon Pilgrim	3
Michael Maitland	3
Nikita Popov	3
Brandon Wu	3

glibc (RISC-V)

Commits

Contributors

Lines Added

Lines Removed

Just a single commit landed in glibc (RISC-V) this month.

1 New features & support

Notable Changes

Linux: Add the sched_setattr and sched_getattr functions (21571ca0d7, Florian Weimer)

Top Contributors

Author	Commits
Florian Weimer	1

Binutils (RISC-V)

Commits

Contributors

803

Lines Added

Lines Removed

Minimal activity in Binutils (RISC-V): 4 commits from 3 contributors.

2 ISA extensions 2 New features & support 1 Bug fixes

Notable Changes

RISC-V: Add support for XCVsimd extension in CV32E40P (a6ecb18b79, Mary Bennett)
RISC-V: Add Smrnmi extension csrs. (f0bdf8c169, Jiawei)
RISC-V: odd data padding vs mapping symbols (9a788db16a, Jan Beulich)
RISC-V: correct alignment directive handling for text sections (784e2ef54b, Jan Beulich)

Top Contributors

Author	Commits
Jan Beulich	2
Jiawei	1
Mary Bennett	1

U-Boot (RISC-V)

Commits

Contributors

682

Lines Added

Lines Removed

A quieter month for U-Boot (RISC-V), with 14 commits from 5 contributors. Leading the charge was Chia-Wei Wang with 6 commits.

4 New features & support 1 ISA extensions 1 Bug fixes 1 Device tree / platform support

Notable Changes

riscv: Add AST2700 SoC initial platform support (and 2 more) (9efcb10a09, Chia-Wei Wang)
board: ibex_ast2700: Add FMC header support (73f802ac95, Chia-Wei Wang)
ram: ast2700: Add DRAM controller initialization (a1ad11ce52, Chia-Wei Wang)
riscv: show registers in crash dumps by default (and 2 more) (4a36d217bb, Heinrich Schuchardt)
riscv: dts: sophgo: Replace device clocks with real clocks. (aa4a03f2e2, Kongyang Liu)
riscv: u-boot-spl.lds: Remove _image_binary_end alignment (717002f8ff, Chia-Wei Wang)
riscv: define find_{first,next}_zero_bit in asm/bitops.h (bbbb2ef4a7, Maxim Kochetkov)
lmb: make LMB memory map persistent and global (ed17a33fed, Sughosh Ganu)
board: fix compatible property Milk-V Mars CM (e0495c9186, Heinrich Schuchardt)
lmb: do away with arch_lmb_reserve() (6534d26ee9, Sughosh Ganu)

Top Contributors

Author	Commits
Chia-Wei Wang	6
Heinrich Schuchardt	4
Sughosh Ganu	2
Kongyang Liu	1
Maxim Kochetkov	1

Mailing List Activity

riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards — Hal Feng

Rust (RISC-V)

Commits

Contributors

102

Lines Added

Lines Removed

A quieter month for Rust (RISC-V), with 5 commits from 3 contributors. B I Mohammed Abbas dominated with 3/5 commits (60%). Extension support saw 1 commit covering Zicsr.

4 New features & support 1 ISA extensions

Notable Changes

Reformat using the new identifier sorting from rustfmt (c682aa162b, Michael Goulet)
Update std support for all vxworks target archs (eb6a52c2f6, B I Mohammed Abbas)
Add `warn(unreachable_pub)` to `rustc_target`. (0fb3a509cf, Nicholas Nethercote)
Add Vxworks RISC-V targets (485e90f1a7, B I Mohammed Abbas)
Vxworks riscv target specs: remove redundant zicsr feature (6d229f89ba, B I Mohammed Abbas)

Top Contributors

Author	Commits
B I Mohammed Abbas	3
Michael Goulet	1
Nicholas Nethercote	1

OpenOCD (RISC-V)

Commits

Contributors

Lines Added

Lines Removed

A light month for OpenOCD (RISC-V) with 3 commits from 3 contributors.

1 Bug fixes

Notable Changes

doc/xtensa: update supported architecture list (a9ba96f94a, Ian Thompson)
doc: fix stm32l4x option_write usage (ca72d23c3b, Ondřej Hošek)
server/telnet: Restructure commands (ad21613618, Marc Schink)

Top Contributors

Author	Commits
Marc Schink	1
Ian Thompson	1
Ondřej Hošek	1

Linux Kernel Docs & DT (RISC-V)

Commits

Contributors

Lines Added

Lines Removed

A light month for Linux Kernel Docs & DT (RISC-V) with 2 commits from 2 contributors.

2 New features & support 2 Device tree / platform support 1 ISA extensions

Notable Changes

dt-bindings: riscv: Add Svvptc ISA extension description (d25599b593, Alexandre Ghiti)
dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles (fa1823d4e2, Thomas Bonnefille)

Top Contributors

Author	Commits
Alexandre Ghiti	1
Thomas Bonnefille	1