RISC-V Software News

October 2024 — Upstream Open Source Activity

The Big Picture

A strong October for the RISC-V software stack: 356 commits across 13 projects. The most active projects were LLVM (RISC-V) (163), Linux Kernel (RISC-V) (78), QEMU (RISC-V) (56). Software support advanced for Smnpm, Ssnpm, Zacas, Zbkb, Zfh, Zfinx, Zicboz, Zvfh. Virtualisation saw 24 KVM-related patches.

RISC-V International

The spec repos saw 65 commits this month, led by ISA Manual with 32 commits.

Spec Repository Activity

RepositoryCommitsContributors
ISA Manual 32 12
Profiles 18 3
SBI Spec 12 6
Debug Spec 3 2

Linux Kernel (RISC-V)

78
Commits
33
Contributors
2437
Lines Added
397
Lines Removed

Linux Kernel (RISC-V) had a solid month with 78 commits from 33 contributors. Leading the charge was Anup Patel with 13 commits. New feature work included 26 commits: "of/fdt: add dt_phys arg to early_init_dt_scan and early_init_dt_verify"; "RISC-V: KVM: Add common nested acceleration support". Platform and DT work accounted for 20 commits. Virtualisation work accounted for 19 patches, continuing to mature RISC-V KVM support. ISA extension work spanned 8 commits, touching Smnpm, Ssnpm, Zicboz.

26 New features & support 20 Device tree / platform support 19 KVM / Virtualisation 8 ISA extensions 8 Interrupt controllers (AIA/APLIC/PLIC) 5 Bug fixes 3 Performance optimisations 2 Vector extension (RVV) 1 Cleanup & refactoring

Notable Changes

  • RISC-V: Add defines for the SBI nested acceleration extension (5daf89e73d, Anup Patel)
  • riscv: KVM: add basic support for host vs guest profiling (eded6754f3, Quan Zhou)
  • riscv: defconfig: enable gpio support for TH1520 (5fb0ecf73e, Drew Fustini)
  • riscv: dts: sophgo: cv1812h: add pinctrl support (30003e3f80, Inochi Amaoto)
  • riscv: dts: sophgo: cv1800b: add pinctrl support (23c7816ddd, Inochi Amaoto)
  • riscv, bpf: Fix possible infinite tailcall when CONFIG_CFI_CLANG is enabled (30a59cc797, Pu Lehui)
  • asm-generic: provide generic page_to_phys and phys_to_page implementations (c5c3238d9b, Christoph Hellwig)
  • riscv: dts: sophgo: Add SARADC description for Sophgo CV1800B (and 2 more) (45a544a62e, Thomas Bonnefille)
  • of/fdt: add dt_phys arg to early_init_dt_scan and early_init_dt_verify (b2473a3597, Usama Arif)
  • riscv: Allow ptrace control of the tagged address ABI (and 7 more) (78844482a1, Samuel Holland)
  • RISC-V: Report vector unaligned access speed hwprobe (and 4 more) (e7c9d66e31, Jesse Taube)
  • arm64: dts: renesas: rzg2ul-smarc-som: Enable serial NOR flash (c0f2ec5683, Biju Das)
  • riscv: dts: thead: Add missing GPIO clock-names (and 5 more) (bcec43a092, Emil Renner Berthing)
  • drivers/perf: riscv: Align errno for unsupported perf event (c625154993, Pu Lehui)
  • irqchip/sifive-plic: Unmask interrupt in plic_irq_enable() (6b1e0651e9, Nam Cao)

Top Contributors

AuthorCommits
Anup Patel13
Samuel Holland10
Emil Renner Berthing7
Jesse Taube5
Alexandre Ghiti4
Sean Christopherson3
Thomas Bonnefille3
Quan Zhou2
Chunyan Zhang2
Conor Dooley2

OpenSBI

20
Commits
5
Contributors
639
Lines Added
214
Lines Removed

A steady month for OpenSBI with 20 commits from 5 contributors. Leading the charge was Anup Patel with 9 commits. New feature work included 6 commits: "lib: sbi: add Smdbltrp ISA extension support"; "lib: sbi: implement firmware feature SBI_FWFT_DOUBLE_TRAP". AIA and interrupt controller work accounted for 2 patches. Virtualisation work accounted for 1 patch, continuing to mature RISC-V KVM support.

6 New features & support 2 ISA extensions 2 Interrupt controllers (AIA/APLIC/PLIC) 1 KVM / Virtualisation 1 Bug fixes 1 Performance optimisations 1 Device tree / platform support

Notable Changes

  • lib: sbi: add Smdbltrp ISA extension support (and 6 more) (c46a937fd9, Clément Léger)
  • lib: sbi: Add support to mask/unmask SSE events (b919daf495, Himanshu Chauhan)
  • lib: sbi_domain: Make sbi_domain_root_add_memregion() as local function (36c1e4064f, Anup Patel)
  • lib: sbi_domain: Use domain data support for per-domain hart context (f609fd8584, Anup Patel)
  • lib: utils/ipi: Use sbi_domain_root_add_memrange() for ACLINT mswi (8576ca4234, Anup Patel)
  • lib: utils/irqchip: Use sbi_domain_root_add_memrange() for APLIC (dc5d747af8, Anup Patel)
  • lib: utils/irqchip: Use sbi_domain_root_add_memrange() for IMSIC (abc68e881d, Anup Patel)
  • docs: Remove hartindex_to_context_table from domain_support.md (ebbd276146, Anup Patel)
  • include: sbi: Optimize reads of mhartid and mscratch (62447cd7aa, Samuel Holland)
  • lib: sbi: Introduce domain data (81d79913a0, Anup Patel)
  • lib: utils/fdt: Use sbi_domain_memregion_init() when parsing domains (2d517fce9b, Anup Patel)
  • include: sbi: Remove cyclic include in sbi_domain_context.h (65d4e9be95, Anup Patel)
  • lib: utils/gpio: designware: Allocate chips on the heap (3e0c170397, Samuel Holland)
  • lib: sbi: fix number of PMP entries detection (1a2e507d23, Vladimir Kondratiev)

Top Contributors

AuthorCommits
Anup Patel9
Clément Léger7
Samuel Holland2
Vladimir Kondratiev1
Himanshu Chauhan1

Notable Discussions

QEMU (RISC-V)

56
Commits
20
Contributors
4314
Lines Added
168
Lines Removed

A productive month for QEMU (RISC-V) with 56 commits from 20 contributors. Leading the charge was Deepak Gupta with 20 commits. New feature work included 24 commits: "hw/riscv/riscv-iommu: add DBG support"; "hw/riscv/riscv-iommu: add ATS support". Bug fixes accounted for 9 commits (16%). Virtualisation work accounted for 4 patches, continuing to mature RISC-V KVM support.

24 New features & support 15 ISA extensions 9 Bug fixes 4 KVM / Virtualisation 2 Interrupt controllers (AIA/APLIC/PLIC) 1 Vector extension (RVV) 1 Cleanup & refactoring

Notable Changes

  • target: riscv: Add Svvptc extension support (5b8764193b, Alexandre Ghiti)
  • target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension (af0b5b7b2a, Maria Klauchek)
  • target/riscv: Enable RV32 CPU support in RV64 QEMU (and 5 more) (e087bd4de3, TANG Tiancheng)
  • hw/riscv/riscv-iommu: add DBG support (and 2 more) (a7aa525b93, Tomasz Jeznach)
  • disas/riscv: enable disassembly for compressed sspush/sspopchk (and 2 more) (e75f945123, Deepak Gupta)
  • target/riscv: Expose zicfiss extension as a cpu property (and 16 more) (a6a47319dd, Deepak Gupta)
  • target/riscv: Preliminary textra trigger CSR writting support (c4db48cc24, Alvin Chang)
  • target/riscv: Add textra matching condition for the triggers (6ffe9b6669, Alvin Chang)
  • hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug (df240d66ef, Tomasz Jeznach)
  • hw/riscv: add riscv-iommu-pci reference device (and 2 more) (b9b283260e, Tomasz Jeznach)
  • target: riscv: Enable Bit Manip for OpenTitan Ibex CPU (06fb3bda6a, Alistair Francis)
  • target/riscv: Add a property to set vl to ceil(AVL/2) (12f1e2ec00, Jason Chien)
  • target/riscv32: Fix masking of physical address (b27402813e, Andrew Jones)
  • target/riscv: Add max32 CPU for RV64 QEMU (48cea772c3, LIU Zhiwei)
  • target/riscv/cpu_helper: Fix linking problem with semihosting disabled (177060d860, Thomas Huth)

Top Contributors

AuthorCommits
Deepak Gupta20
Tomasz Jeznach7
TANG Tiancheng6
Daniel Henrique Barboza3
Andrew Jones3
Bernhard Beschow2
Alvin Chang2
Anton Blanchard1
Rob Bradford1
LIU Zhiwei1

LLVM (RISC-V)

163
Commits
38
Contributors
45594
Lines Added
33138
Lines Removed

LLVM (RISC-V) saw heavy activity with 163 commits from 38 contributors. A hefty +45,594/-33,138 line diff. Craig Topper was the most active contributor with 42 commits. Backend and code generation work was the biggest theme at 40 commits. New feature work included 40 commits: "[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274)"; "[RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might read FRM. (#114186)". ISA extension work spanned 17 commits, touching Zbkb, Zfh, Zfinx, Zvfh, Zvfhmin.

40 Compiler backend / code generation 40 New features & support 38 Cleanup & refactoring 17 ISA extensions 15 Bug fixes 13 Vector extension (RVV) 4 Performance optimisations

Notable Changes

  • [RISCV] Add missing hasPostISelHook = 1 to vector pseudos that might read FRM. (#114186) (71b6f6b8a1, Craig Topper)
  • [RISCV][VLOPT] Update test cases to use riscv-enable-vl-optimizer and better formatting (a31e834ba8, Michael Maitland)
  • Reapply "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112203) (854ded9b24, c8ef)
  • Revert "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112200) (a3b0c31ebc, c8ef)
  • [RISCV][VLOPT] Add support for integer widening multiply instructions (#112204) (658ff0b84c, Michael Maitland)
  • [DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes. (#111774) (11f625cb87, c8ef)
  • [RISCV] Add lowering for @llvm.experimental.vector.compress (#113291) (b799cc3418, Pengcheng Wang)
  • [RISCV] Add OperandType for vector rounding mode operands. (#114179) (c3724ba866, Craig Topper)
  • [RISCV][VLOPT] Add support for 11.9 min/max instructions (#112198) (82e89c0271, Michael Maitland)
  • [RISCV][VLOPT] Add support for 11.11 div instructions (#112201) (c2c4db8d8f, Michael Maitland)
  • [RISCV] Sink hasPostISelHook = 1 for vector pseudos into the subclasses that set HasRoundModeOp. NFC (#114294) (51628faa01, Craig Topper)
  • Revert "[RISCV][TTI] Recognize CONCAT_VECTORS if a shufflevector mask is multiple insert subvector. (#110457)" (f11568bcb0, Philip Reames)
  • [RISCV] Add support for inline asm constraint vd (#111653) (dba54fb074, Jim Lin)
  • [RISCV][VLOPT] Enable VLOptimizer for vl-opt.ll test file (2f077ece2f, Michael Maitland)
  • [RISCV] Add Supm extension to RVA23 profiles (#113619) (cbdfb18794, Alex Bradbury)

Top Contributors

AuthorCommits
Craig Topper42
Luke Lau22
Michael Maitland18
Fangrui Song15
Alex Bradbury10
Yingwei Zheng7
Sam Elliott7
Brandon Wu4
Philip Reames3
c8ef3

glibc (RISC-V)

2
Commits
2
Contributors
1
Lines Added
8
Lines Removed

glibc (RISC-V) was quiet this month with 2 commits from 2 contributors.

1 Bug fixes

Notable Changes

  • replace tgammaf by the CORE-MATH implementation (392b3f0971, Paul Zimmermann)
  • riscv: align .preinit_array (bug 32228) (a36814e145, Andreas Schwab)

Top Contributors

AuthorCommits
Paul Zimmermann1
Andreas Schwab1

Notable Discussions

Binutils (RISC-V)

7
Commits
4
Contributors
19
Lines Added
18
Lines Removed

Binutils (RISC-V) saw lighter activity with 7 commits from 4 contributors. Top contributor: Alan Modra with 4 commits. Work on Zacas accounted for 1 commit.

1 ISA extensions 1 Bug fixes 1 New features & support

Notable Changes

  • RISC-V: Dump instruction without checking architecture support as usual. (004a5bfc72, Nelson Chu)
  • Revert "is_target_special_symbol fixes for commit 68bbe1183379" (e022977bc5, Alan Modra)
  • is_target_special_symbol fixes for commit 68bbe1183379 (6e40f9bb31, Alan Modra)
  • gas: constify md_{short,long}opts and md_longopts_size (641cf0e2c0, Jan Beulich)
  • Revised "Don't return (null) from bfd_elf_sym_name" (124deb3101, Alan Modra)
  • RISC-V: Fix implicit dependency of Zabha and Zacas (542d8137f9, Xiao Zeng)
  • Replace uses of asprintf with xasprintf (86b26b453f, Alan Modra)

Top Contributors

AuthorCommits
Alan Modra4
Nelson Chu1
Jan Beulich1
Xiao Zeng1

GDB (RISC-V)

2
Commits
1
Contributors
2
Lines Added
2
Lines Removed

GDB (RISC-V) was quiet this month with 2 commits. Andrew Burgess was the driving force, authoring 2 of 2 commits (100%).

Notable Changes

  • Revert "gdbserver: pass osabi to GDB in target description" (a9ed7a0814, Andrew Burgess)
  • gdbserver: pass osabi to GDB in target description (98bcde5e26, Andrew Burgess)

Top Contributors

AuthorCommits
Andrew Burgess2

U-Boot (RISC-V)

17
Commits
9
Contributors
187
Lines Added
875
Lines Removed

U-Boot (RISC-V) saw moderate activity with 17 commits from 9 contributors. A net deletion month (+187/-875) — always satisfying. Top contributor: Simon Glass with 6 commits. Board and device tree support got 5 commits.

5 New features & support 5 Device tree / platform support 3 Cleanup & refactoring 1 ISA extensions

Notable Changes

  • riscv: Add support for defining instructions (bfc8ca3f7f, Mayuresh Chitale)
  • cmd: sbi: Add FWFT, MPXY extensions (faf82cc695, Heinrich Schuchardt)
  • riscv: qemu: Explicitly advertise RVVM support (f5c6ac8aaf, LekKit)
  • riscv: add missing linefeed in error message (c1558743bf, Heinrich Schuchardt)
  • riscv: cache: Add CBO instructions (9e859849e2, Mayuresh Chitale)
  • riscv64: dts: starfive: Star64 ethernet0 phy delay values sync with upstream Linux (8d2a6d46d1, E Shattow)
  • riscv64: dts: starfive: Mars ethernet0 phy delay values sync with upstream Linux (b8db88ab58, E Shattow)
  • board: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD (dac3ce976a, Simon Glass)
  • arch: Use CONFIG_XPL_BUILD instead of CONFIG_SPL_BUILD (bef9fdbed2, Simon Glass)
  • efi_loader: Rename and move CMD_BOOTEFI_HELLO_COMPILE (6fe80876dc, Simon Glass)
  • efi: arm: x86: riscv: Drop crt0/relocal extra- rules (69616cec72, Simon Glass)
  • riscv: dts: mpfs: migrate to OF_UPSTREAM (239e470509, Conor Dooley)
  • riscv: resume needs to be a global (8e1acda14e, Anton Blanchard)
  • global: Rename SPL_TPL_ to PHASE_ (5c10c8badf, Simon Glass)
  • riscv: mbv: Align DT with QEMU (9d688e6da5, Michal Simek)

Top Contributors

AuthorCommits
Simon Glass6
Mayuresh Chitale2
E Shattow2
Heinrich Schuchardt2
Conor Dooley1
Anton Blanchard1
Michal Simek1
LekKit1
Marek Vasut1

Rust (RISC-V)

6
Commits
3
Contributors
203
Lines Added
7
Lines Removed

A quieter month for Rust (RISC-V), with 6 commits from 3 contributors. Henri Lunnikivi dominated with 4/6 commits (66%).

3 New features & support

Notable Changes

  • Add platform support doc for rv32e (6edd0b356f, Henri Lunnikivi)
  • Add targets: riscv32{e|em|emc} (b22b348e0d, Henri Lunnikivi)
  • Add comment: data_layout (7a0bac49c8, Henri Lunnikivi)
  • riscv-soft-abi-with-float-features.rs: adapt for LLVM 20 (e4f793a1aa, Krasimir Georgiev)
  • Always specify `llvm_abiname` for RISC-V targets (3ea91c05db, beetrees)
  • Update target fns to latest main (04099b663c, Henri Lunnikivi)

Top Contributors

AuthorCommits
Henri Lunnikivi4
Krasimir Georgiev1
beetrees1

OpenOCD (RISC-V)

2
Commits
1
Contributors
125
Lines Added
125
Lines Removed

Minimal activity in OpenOCD (RISC-V): 2 commits. Most of the work came from Antonio Borneo (2 of 2 commits, 100%).

Notable Changes

  • target: riscv: convert 'unsigned' to 'unsigned int' (957eb741a0, Antonio Borneo)
  • target: riscv: remove non-trivial 'unsigned' cast (fec3b22421, Antonio Borneo)

Top Contributors

AuthorCommits
Antonio Borneo2

musl libc (RISC-V)

1
Commits
1
Contributors
1
Lines Added
2
Lines Removed

musl libc (RISC-V) had exactly one commit this month.

Notable Changes

  • wire up vdso clock_gettime for riscv32 and riscv64 (9b6a24f9c5, Rich Felker)

Top Contributors

AuthorCommits
Rich Felker1

OpenBLAS (RISC-V)

1
Commits
1
Contributors
0
Lines Added
2
Lines Removed

OpenBLAS (RISC-V) had exactly one commit this month. Code housekeeping was a significant theme at 1 commit (100%).

1 Cleanup & refactoring

Notable Changes

  • remove unused INLINE macro definitions (815cb24944, TGY)

Top Contributors

AuthorCommits
TGY1

Linux Kernel Docs & DT (RISC-V)

1
Commits
1
Contributors
18
Lines Added
0
Lines Removed

One lone commit for Linux Kernel Docs & DT (RISC-V) this month.

1 ISA extensions 1 New features & support 1 Device tree / platform support

Notable Changes

  • dt-bindings: riscv: Add pointer masking ISA extensions (8727163a1a, Samuel Holland)

Top Contributors

AuthorCommits
Samuel Holland1