RISC-V Software News

Spec Repository Activity

Notable Changes

• RISC-V: KVM: Add Svade and Svadu Extensions Support for Guest/VM (97eccf7db4, Yong-Xuan Wang)
• RISC-V: Add Svade and Svadu Extensions Support (94a7734d09, Yong-Xuan Wang)
• riscv: dts: sophgo: Add emmc support for Huashan Pi (b5cf65cc0f, Inochi Amaoto)
• riscv: Add qspinlock support (and 8 more) (ab83647fad, Alexandre Ghiti)
• riscv: add PREEMPT_LAZY support (22aaec357c, Jisheng Zhang)
• kbuild: add $(objtree)/ prefix to some in-kernel build artifacts (214c0eea43, Masahiro Yamada)
• riscv: dts: sophgo: Add sdio configuration for Huashan Pi (06133f48a8, Inochi Amaoto)
• riscv: defconfig: Enable T-HEAD C900 ACLINT SSWI drivers (6da33567c0, Inochi Amaoto)
• arch: introduce set_direct_map_valid_noflush() (0c6378a715, Mike Rapoport (Microsoft))
• riscv: dts: thead: Add TH1520 ethernet nodes (7e756671a6, Emil Renner Berthing)
• riscv: dts: sophgo: fix pinctrl base-address (44196383a2, Thomas Bonnefille)
• asm-generic: introduce text-patching.h (0c3beacf68, Mike Rapoport (Microsoft))
• irqchip/riscv-aplic: Prevent crash when MSI domain is missing (1f181d1cda, Samuel Holland)
• RISC-V: KVM: Fix APLIC in_clrip and clripnum write emulation (60821fb4dd, Yong-Xuan Wang)
• vdso: Rename struct arch_vdso_data to arch_vdso_time_data (a812eee0b6, Nam Cao)

Notable Changes

• platform: ensure enough heap size with debug triggers extension (dcb68dd17d, Inochi Amaoto)
• lib: utils/fdt: Add helpers for generic driver initialization (1ccc52c427, Samuel Holland)
• platform: introduce DT-based configurable heap size (5d4e3fb2ee, Inochi Amaoto)
• top: Add .editorconfig to set basic coding styles (369c64517e, Hui Min Mina Chou)
• docs: add example of building the Linux kernel (701948bdec, Tim Hutt)
• Makefile: enable --gc-sections (0171cfcc70, Kele Zhang)
• lib: sbi_irqchip: Set the IRQ handler when registering a chip (and 2 more) (111772353f, Samuel Holland)
• lib: utils/irqchip: Move per-hart data from fdt_plic to plic (and 4 more) (56fddce83f, Samuel Holland)
• lib: utils/gpio: Use fdt_driver for initialization (and 2 more) (bef8f9b806, Samuel Holland)
• platform: Drop irqchip warm init and exit hooks (and 2 more) (678f5909a3, Samuel Holland)
• lib: sbi_ipi: Make .ipi_clear always target the current hart (be9752a071, Samuel Holland)
• treewide: Make carray arrays const and NULL-terminated (df1c100001, Samuel Holland)
• lib: sbi_ipi: Move initial IPI clear to sbi_ipi_init() (693afc818f, Samuel Holland)
• lib: utils/serial: Use fdt_driver for initialization (a524f0a507, Samuel Holland)
• lib: utils/regmap: Use fdt_driver for initialization (1f8db2f18f, Samuel Holland)

Notable Changes

• target/riscv: Set vdata.vm field for vector load/store whole register instructions (b48381b1ee, Max Chou)
• target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions (and 4 more) (e32988789b, Max Chou)
• target/riscv: Inline unit-stride ld/st and corresponding functions for performance (f8ee6f533d, Max Chou)
• hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check (d3b96a5319, Daniel Henrique Barboza)
• target/riscv/kvm: Update kvm exts to Linux v6.11 (13d438502b, Quan Zhou)
• hw/riscv/riscv-iommu: change 'depth' to int (cd5d265f42, Daniel Henrique Barboza)
• hw/riscv/iommu: fix build error with clang (d37eede7a8, Pierrick Bouvier)

Notable Changes

• RISC-V: Add intrinsics support for SiFive Xsfvqmaccqoq/dod extensions. (356bfe8ca1, yulong)
• RISC-V: Minimal support for svvptc extension. (e4f4b2dc08, Dongyan Chen)
• [RISC-V][PR target/117690] Add missing shift in constant synthesis (9b7917b34f, Jeff Law)
• [PATCH v7 03/12] RISC-V: Add CRC expander to generate faster CRC. (74eb3570e6, Mariam Arutunian)
• [RISC-V][PR target/116590] Avoid emitting multiple instructions from fmacc patterns (41fb3a5669, Jeff Law)
• [RISC-V][PR target/109279] Improve RISC-V constant synthesis (df2e832c90, Jeff Law)
• RISC-V: Ensure vtype for full-register moves [PR117544]. (b82a5810e7, Robin Dapp)
• RISC-V: avlprop: Do not propagate VL from slidedown. (9c82afd42e, Robin Dapp)
• diagnostics: replace %<%s%> with %qs [PR104896] (9f06b910a8, David Malcolm)
• Regeernate .opt.urls after nios2 removal (9afcbc2dd3, Andrew Pinski)
• opt.url: Regenerate the .opt.urls files (cc0f32274d, Andrew Pinski)
• build: Remove INCLUDE_MEMORY [PR117737] (b3f1b9e2aa, Andrew Pinski)
• __builtin_prefetch fixes [PR117608] (f7bbdf7e4a, Jakub Jelinek)
• RISC-V: Use dynamic shadow offset (c84a8a274a, Kito Cheng)

Notable Changes

• Revert "[DAGCombiner] Add support for scalarising extracts of a vector setcc (#116031)" (#117556) (9b76e7fc60, David Sherwood)
• [DAGCombiner] Add support for scalarising extracts of a vector setcc (#116031) (22ec44f509, David Sherwood)
• [RISCV] Add an implementation of findRepresentativeClass to assign i32 to GPRRegClass for RV64. (#116165) (900c056531, Craig Topper)
• [RISCV] Add additional CHECK prefixes to fixed-vectors-strided-load-store-asm.ll. NFC (2187738508, Craig Topper)
• [RISCV] Enable scalable loop vectorization for zvfhmin/zvfbfmin (#115272) (b2e2d8b3f6, Luke Lau)
• [RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114014) (93caee17ad, Mark Goncharov)
• [RISCV] Add Qualcomm uC Xqcisls (Scaled Load Store) extension (#117987) (8fcbba82d6, Sudharsan Veeravalli)
• [RISCV][GISel] Support s32/s64 G_FSUB/FDIV/FNEG without F/D extensions. (bb5bbe523d, Craig Topper)
• [RISCV][GISel] Remove s32 support for G_ADD/SUB/AND/OR/XOR on RV64. (c280522f7e, Craig Topper)
• [RISCV] Add coverage for recently added vectorization intrinsics (1f342f94b2, Philip Reames)
• [DAGCombiner] Add basic support for `trunc nsw/nuw` (#113808) (f74aed7938, Yingwei Zheng)
• [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169) (c4645ffeda, Sudharsan Veeravalli)
• [RISCV] Add explicit VLS test line for vector spill/fill (6da8ff82a8, Philip Reames)
• [RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC (f4270045f4, Craig Topper)
• [RISCV] Add +optimized-nfN-segment-load-store (#114414) (beb12f92c7, Luke Lau)

Notable Changes

• RISC-V: Use builtin for copysign and copysignf (d2264de5db, Julian Zhu)
• math: Use tanf from CORE-MATH (and 10 more) (bccb0648ea, Adhemerval Zanella)
• RISC-V: Use builtin for fma and fmaf (32445b6dd2, Julian Zhu)

Notable Changes

• RISC-V: Support SiFive extensions: xsfvqmaccdod, xsfvqmaccqoq and xsfvfnrclipxfqf (595e49a4b7, Nelson Chu)
• RISC-V: Add Zcmt instructions and csr. (00ef37e860, Jiawei)
• RISC-V: Don't report warnings when linking different privileged spec objects. (cb45bd5948, Nelson Chu)
• opcodes: fix Werror=format build breaker in opcodes/riscv-dis.c (6206516653, Tom de Vries)

Notable Changes

• gdbserver: pass osabi to GDB in more target descriptions (1048062a3f, Andrew Burgess)
• gdbserver: remove lwpid_of(thread) (5929ef8975, Simon Marchi)

Notable Changes

• dm: Add dm_remove_devices_active() for ordered device removal (dabaa4ae32, Janne Grunau)
• riscv: Introduce configuration for 64bit version Microblaze V (d5f5e77818, Michal Simek)

Notable Changes

• tests: use `max-llvm-major-version` instead of `ignore-llvm-version` range like `N - 99` (91fa16b211, 许杰友 Jieyou Xu (Joe))
• Update linux_musl base to dynamically link the crt by default (9c37c14aa2, Wesley Wiser)

Notable Changes

• stlink: deprecate HLA support (34ec5536c0, Antonio Borneo)
• target: riscv: convert 'unsigned' to 'unsigned int' (134e56338d, Mark Zhuang)

Notable Changes

• dt-bindings: riscv: Add Ziccrse ISA extension description (447b2afbcd, Alexandre Ghiti)
• dt-bindings: riscv: Add Zabha ISA extension description (51624ddcf5, Alexandre Ghiti)
• dt-bindings: riscv: Add Svade and Svadu Entries (b8d4816717, Yong-Xuan Wang)