A strong December for the RISC-V software stack: 364 commits across 12 projects. The most active projects were LLVM (RISC-V) (166), QEMU (RISC-V) (46), OpenSBI (42). Virtualisation saw 12 KVM-related patches.
RISC-V International
The spec repos saw 22 commits this month, led by ISA Manual with 10 commits.
Spec Repository Activity
Repository
Commits
Contributors
ISA Manual
10
10
SBI Spec
4
3
ELF psABI
4
3
Debug Spec
3
3
Profiles
1
1
Linux Kernel (RISC-V)
31
Commits
17
Contributors
295
Lines Added
94
Lines Removed
A steady month for Linux Kernel (RISC-V) with 31 commits from 17 contributors. Masami Hiramatsu (Google) was the most active contributor with 6 commits. New feature work included 11 commits: "RISC-V: KVM: Add new exit statstics for redirected traps"; "RISC-V: KVM: Add SBI system suspend support". KVM and virtualisation received 9 patches.
11 New features & support9 KVM / Virtualisation3 ISA extensions3 Bug fixes3 Device tree / platform support2 Performance optimisations1 Interrupt controllers (AIA/APLIC/PLIC)
Notable Changes
riscv: defconfig: enable pinctrl and dwmac support for TH1520 (e7177ecdd2, Drew Fustini)
riscv: defconfig: enable pinctrl and dwmac support for TH1520 (0207244ea0, Drew Fustini)
RISC-V: KVM: Add new exit statstics for redirected traps (af79caa83f, Atish Patra)
RISC-V: KVM: Add SBI system suspend support (023c15151f, Andrew Jones)
lib/crc32: expose whether the lib is really optimized at runtime (and 2 more) (b5ae12e0ee, Eric Biggers)
tracing: Add ftrace_partial_regs() for converting ftrace_regs to pt_regs (b9b55c8912, Masami Hiramatsu (Google))
riscv: dts: starfive: jh7110-pine64-star64: enable usb0 host function (03bd268ae0, E Shattow)
riscv: dts: starfive: jh7110-milkv-mars: enable usb0 host function (708d55db3e, E Shattow)
A productive month for OpenSBI with 42 commits from 11 contributors. Top contributor: Anup Patel with 14 commits. New feature work included 21 commits: "top: add ~ files to .gitignore"; "Makefile: Don't enable V-extension using -march option". AIA and interrupt controller work accounted for 10 patches. Bug fixes accounted for 7 commits (16%). Board and device tree support got 6 commits.
21 New features & support10 Interrupt controllers (AIA/APLIC/PLIC)7 Bug fixes6 Device tree / platform support3 ISA extensions1 Vector extension (RVV)1 Compiler backend / code generation1 Cleanup & refactoring
Notable Changes
lib/utils: Add RPMI messaging protocol and shared memory transport support (91f46fb47e, Rahul Pathak)
lib: sbi_misaligned_ldst: Add handling of vector load/store (c2acc5e5b0, Nylon Chen)
Makefile: Don't enable V-extension using -march option (5545602f77, Anup Patel)
A productive month for QEMU (RISC-V) with 46 commits from 14 contributors. Daniel Henrique Barboza was the most active contributor with 13 commits. New feature work included 18 commits: "target/riscv: add support for RV64 Xiangshan Nanhu CPU"; "target/riscv: add ssstateen". Interrupt controller infrastructure (AIA/APLIC/PLIC/IMSIC) received 4 patches. KVM and virtualisation received 2 patches.
18 New features & support5 ISA extensions4 Interrupt controllers (AIA/APLIC/PLIC)2 KVM / Virtualisation2 Bug fixes2 Cleanup & refactoring1 Compiler backend / code generation1 Device tree / platform support
Notable Changes
target/riscv: add support for RV64 Xiangshan Nanhu CPU (2fc8f50ead, MollyChen)
hw/riscv/virt.c, riscv-iommu-sys.c: add MSIx support (01c1caa9d1, Daniel Henrique Barboza)
hw/riscv: Add the checking if DTB overlaps to kernel or initrd (and 2 more) (1a65064c1f, Jim Shu)
hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format (6ab861421c, Sia Jee Heng)
hw/intc/riscv_aplic: add kvm_msicfgaddr for split mode aplic-imsic (e0c87e3067, Daniel Henrique Barboza)
hw/riscv/virt: Add IOMMU as platform device if the option is set (2c12de1460, Sunil V L)
target/riscv: Check svukte is not enabled in RV32 (and 5 more) (19d476ff13, Fea.Wang)
target/riscv: Include missing headers in 'vector_internals.h' (04480a0e22, Philippe Mathieu-Daudé)
hw/riscv/virt.c, riscv_aplic.c: add 'emulated_aplic' helpers (b319ef15b8, Daniel Henrique Barboza)
hw/riscv/riscv-iommu.c: add riscv_iommu_instance_init() (4876e6f7b5, Daniel Henrique Barboza)
hw/riscv/riscv-iommu: implement reset protocol (9afd26715e, Daniel Henrique Barboza)
hw/riscv: add riscv-iommu-sys platform device (5b128435dc, Tomasz Jeznach)
target/riscv: Add Tenstorrent Ascalon CPU (997570359e, Anton Blanchard)
hw/riscv: Add Microblaze V generic board (77aad42ee2, Sai Pavan Boddu)
target/riscv: add ssstateen (c3de19c0cc, Daniel Henrique Barboza)
GCC (RISC-V) kept moving with 32 commits from 12 contributors. Robin Dapp was the most active contributor with 8 commits. New feature work included 12 commits: "[PATCH v2 2/2] RISC-V: Add Tenstorrent Ascalon 8 wide architecture"; "RISC-V: Add new constraint R for register even-odd pairs". Compiler backend and code generation improvements accounted for 10 commits. RVV work continued with 5 commits touching vector-related code.
12 New features & support10 Compiler backend / code generation6 Cleanup & refactoring5 Vector extension (RVV)5 Bug fixes1 ISA extensions1 Performance optimisations
Notable Changes
RISC-V: Add intrinsics support for SiFive Xsfvfnrclipxfqf extensions. (1352d4dd09, yulong)
RISC-V: Add new constraint R for register even-odd pairs (and 4 more) (fcbb8456a5, Kito Cheng)
[RISC-V][PR target/118122] Fix modes in recently added risc-v pattern (64d31343d4, Jeff Law)
Plenty of action in LLVM (RISC-V) this month: 166 commits from 37 contributors. +28,388/-10,972 lines changed — a big diff. Craig Topper was the most active contributor with 55 commits. Code generation improvements dominated with 66 commits. New feature work included 63 commits: "[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533)"; "[RISCV][VLOPT] Add getOperandInfo for saturating signed multiply (#120351)". RVV work continued with 14 commits touching vector-related code.
66 Compiler backend / code generation63 New features & support27 Cleanup & refactoring14 Vector extension (RVV)11 Bug fixes10 ISA extensions5 Performance optimisations1 KVM / Virtualisation
Notable Changes
[RISCV][VLOPT] Add vector mask producing integer instructions to isSupportedInstr and getOperandInfo (#119733) (7442be68f7, Michael Maitland)
Reapply "[DAGCombiner] Add support for scalarising extracts of a vector setcc (#117566)" (#118823) (8630a7ba7c, David Sherwood)
[RISCV][VLOPT] Add vector narrowing integer right shift instructions to isSupportedInstr (#119602) (412ab602f1, Michael Maitland)
[RISCV][VLOPT] Add support for bitwise logical, single width shift, and vector move (#119412) (9bb29c3dc1, Michael Maitland)
Revert "[DAGCombiner] Add support for scalarising extracts of a vector setcc" (#118693) (d57892a2a1, Vitaly Buka)
[DAGCombiner] Add support for scalarising extracts of a vector setcc (#117566) (4675db5f39, David Sherwood)
[DAGCombine] Remove oneuse restrictions for RISCV in folding (shl (add_nsw x, c1)), c2) and folding (shl(sext(add x, c1)), c2) in some scenarios (#101294) (3083acc215, LiqinWeng)
[RISCV][VLOPT] Add support for mask-register logical instructions and set mask instructions (#112231) (d99c9994db, Michael Maitland)
[RISCV][GISel] Enable support for ArrayType arguments if the element type is also supported. (41c33cbf36, Craig Topper)
[RISCV][TTI] Model the cost of insert/extractelt when the vector split into multiple register group and idx exceed single group. (#118401) (a674209432, Elvis Wang)
[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533) (f590963db8, Philipp van Kempen)
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968) (03847f19f2, Sergei Barannikov)
[RISCV][VLOPT] Add support for more instructions in vl-opt-op-info.mir (#119416) (904849f297, Michael Maitland)
[RISCV][GISel] Support f64->f32 fptrunc and f32->f64 fpext without D extension. (9692242f51, Craig Topper)
Top Contributors
Author
Commits
Craig Topper
55
Michael Maitland
20
Philip Reames
16
Luke Lau
9
Pengcheng Wang
6
Luke Quinn
5
Djordje Todorovic
5
LiqinWeng
5
Sergei Barannikov
3
Sam Elliott
3
glibc (RISC-V)
20
Commits
3
Contributors
196
Lines Added
121
Lines Removed
glibc (RISC-V) saw moderate activity with 20 commits from 3 contributors. Leading the charge was Adhemerval Zanella with 11 commits. New feature work included 9 commits: "Implement C23 atan2pi"; "Implement C23 atanpi".
9 New features & support
Notable Changes
nptl: Add for RISC-V (8dd1588794, Michael Jeanson)
nptl: add RSEQ_SIG for RISC-V (d3b3a12258, Michael Jeanson)
Implement C23 atan2pi (3374de9038, Joseph Myers)
Implement C23 atanpi (ffe79c446c, Joseph Myers)
Implement C23 asinpi (f962932206, Joseph Myers)
Implement C23 acospi (28d102d15c, Joseph Myers)
Implement C23 tanpi (f9e90e4b4c, Joseph Myers)
Implement C23 sinpi (776938e8b8, Joseph Myers)
Implement C23 cospi (0ae0af68d8, Joseph Myers)
math: Use tanhf from CORE-MATH (and 9 more) (0e0be3ed80, Adhemerval Zanella)
A light month for Binutils (RISC-V) with 4 commits from 3 contributors.
1 ISA extensions1 New features & support
Notable Changes
RISC-V: Add support for ssdbltrp and smdbltrp extension. (69a91bcd6e, Dongyan Chen)
RISC-V: PR27566, consider ELF_MAXPAGESIZE/COMMONPAGESIZE for gp relaxations. (6f8e75592c, Nelson Chu)
Remove _bfd_elf_link_hash_table_init target_id param (f92b077ee7, Alan Modra)
Remove bfd_elf_allocate_object object_id param (aa7a348b2f, Alan Modra)
Top Contributors
Author
Commits
Alan Modra
2
Nelson Chu
1
Dongyan Chen
1
GDB (RISC-V)
1
Commits
1
Contributors
12
Lines Added
12
Lines Removed
GDB (RISC-V) had exactly one commit this month.
Notable Changes
Run check-include-guards.py (cc70964032, Tom Tromey)
Top Contributors
Author
Commits
Tom Tromey
1
U-Boot (RISC-V)
14
Commits
5
Contributors
1088
Lines Added
1691
Lines Removed
U-Boot (RISC-V) saw lighter activity with 14 commits from 5 contributors. Notably, more code was removed than added (+1,088/-1,691). Hal Feng was the driving force, authoring 9 of 14 commits (64%). Platform and DT work accounted for 9 commits. New feature work included 8 commits: "riscv: spacemit: bananapi_f3: initial support added"; "riscv: dts: t-head: Add sdhci and emmc nodes".
9 Device tree / platform support8 New features & support1 Bug fixes
Notable Changes
riscv: spacemit: bananapi_f3: initial support added (1cd239f444, Kongyang Liu)
board: add support for LicheeRV Nano (04bcc87f0d, Thomas Bonnefille)
board: starfive: spl: Support multiple DTBs for JH7110 based boards (and 2 more) (8ace850059, Hal Feng)
riscv: dts: jh7110: Support multiple DTBs in a Fit image (and 3 more) (c9489a9d32, Hal Feng)
riscv: dts: sophgo: add device tree for LicheeRV Nano (4897de90c3, Thomas Bonnefille)
riscv: dts: t-head: Add sdhci and emmc nodes (dced3ec324, Maksim Kiselev)
riscv: cpu: jh7110: Sort the list of imply statements (2c1cb8837b, Hal Feng)
fdt: Swap the signature for board_fdt_blob_setup() (fc37a73e66, Simon Glass)
dts: starfive: Switch to using upstream DT (84d3911a01, Hal Feng)
Top Contributors
Author
Commits
Hal Feng
9
Thomas Bonnefille
2
Simon Glass
1
Kongyang Liu
1
Maksim Kiselev
1
Rust (RISC-V)
4
Commits
3
Contributors
20
Lines Added
14
Lines Removed
A light month for Rust (RISC-V) with 4 commits from 3 contributors.
2 Bug fixes1 New features & support
Notable Changes
Mark all Linux/Android/BSD/Fuchsia as supporting "std" in target-spec metadata (e3638e2421, Taiki Endo)
Fix "std" support status of some tier 3 targets (76f9aa1d7e, Taiki Endo)
compiler: Set `target_abi = "ilp32e"` on all riscv32e targets (9a81dc97fb, Jubilee Young)
docs: fix typos (0ebdc0c431, dxsullivan)
Top Contributors
Author
Commits
Taiki Endo
2
dxsullivan
1
Jubilee Young
1
OpenOCD (RISC-V)
1
Commits
1
Contributors
1
Lines Added
1
Lines Removed
OpenOCD (RISC-V) had exactly one commit this month.
1 New features & support
Notable Changes
flash/nor/stm32l4x: Add support for STM32U0 series (66faa420a4, Marc Schink)
Top Contributors
Author
Commits
Marc Schink
1
OpenBLAS (RISC-V)
3
Commits
1
Contributors
269
Lines Added
306
Lines Removed
A light month for OpenBLAS (RISC-V) with 3 commits. Notably, more code was removed than added (+269/-306). tingbo.liao dominated with 3/3 commits (100%). Performance work included 2 commits. The vector extension (RVV) saw 1 commit of continued development.
Optimize the zgemm_tcopy_4_rvv function to be compatible with the situations where the vector lengths(vlens) are 128 and 256. (0bea1cfd9d, tingbo.liao)
Replaced the __riscv_vid_v_i32m2 and __riscv_vid_v_i64m2 with __riscv_vid_v_u32m2 and __riscv_vid_v_u64m2 for riscv64-unknown-linux-gnu-gcc compiling. (d00cc400b1, tingbo.liao)
Optimize the nrm2_rvv function to further improve performance. (c37509c213, tingbo.liao)