RISC-V Software News

Spec Repository Activity

Notable Changes

• riscv: dts: allwinner: Add xtheadvector to the D1/D1s devicetree (ce1daeeba6, Charlie Jenkins)
• riscv: hwprobe: Add thead vendor extension probing (a5ea53da65, Charlie Jenkins)
• riscv: vector: Support xtheadvector save/restore (d863910eab, Charlie Jenkins)
• riscv: add SpacemiT SoC family Kconfig support (8814aa123a, Yangyu Chen)
• riscv: sbi: vendorid_list: Add Microchip Technology to the vendor list (c138285233, Valentina Fernandez)
• mm: pgtable: introduce generic __tlb_remove_table() (and 2 more) (2dccdf7076, Qi Zheng)
• riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3 (3579b3506f, Yixun Lan)
• riscv: dts: spacemit: add Banana Pi BPI-F3 board device tree (d60d57ab6b, Yangyu Chen)
• riscv: add a warning when physical memory address overflows (101971298b, Yunhui Cui)
• riscv: mm: Fix the out of bound issue of vmemmap address (f754f27e98, Xu Lu)
• riscv: csr: Add CSR encodings for CSR_VXRM/CSR_VXSAT (b9a9314424, Charlie Jenkins)
• riscv: dts: add initial SpacemiT K1 SoC device tree (d8fe646919, Yangyu Chen)
• mm/memblock: add memblock_alloc_or_panic interface (c6f239796b, Guo Weikang)
• RISC-V: define the elements of the VCSR vector CSR (66f197785d, Heiko Stuebner)
• riscv: kprobes: Fix incorrect address calculation (13134cc949, Nam Cao)

Notable Changes

• lib: sbi: pmu: add the PMU SSE event only if overflow IRQ is supported (and 5 more) (5c7e2c8334, Clément Léger)
• include: lib: add a simple singly linked list implementation (147978f312, Clément Léger)
• include: utils/fdt_helper: fix typo har't'id (555055d145, Leo Yu-Chi Liang)

Notable Changes

• target/riscv: Add Smdbltrp ISA extension enable switch (and 8 more) (2d8e825928, Clément Léger)
• target/riscv: Add counter delegation/configuration support (and 5 more) (6247dc2ef7, Kaiwen Xue)
• target/riscv: Add Smrnmi cpu extension (and 4 more) (f9653d4eb2, Tommy Wu)
• target/riscv: Add Zicfilp support for Smrnmi (0266fd8b56, Frank Chang)
• target/riscv: Add RISC-V CSR qtest support (1addf57177, Ivan Klokov)
• target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg (and 4 more) (fdb7bce43f, Atish Patra)
• hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache (fa622855ea, Jason Chien)
• target/riscv: Support Supm and Sspm as part of Zjpm v1.0 (and 7 more) (941f76e293, Alexey Baturo)
• target/riscv: add trace in riscv_raise_exception() (and 7 more) (8f1a128942, Daniel Henrique Barboza)
• riscv/gdbstub: add V bit to priv reg (e9952b3631, Yanfeng Liu)
• target/riscv/tcg: add sha (f4df21e07f, Daniel Henrique Barboza)
• target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu (7703a1d1e6, Philippe Mathieu-Daudé)
• target/riscv: rvv: fix typo in vext continuous ldst function names (ffd23ae2a6, Craig Blackmore)
• target/riscv: rvv: speed up small unit-stride loads and stores (d4ce7ef4b3, Craig Blackmore)
• disas/riscv: Guard dec->cfg dereference for host disassemble (f65f3ebfad, LIU Zhiwei)

Notable Changes

• RISC-V: Add a new constraint to ensure that the vl of XTheadVector does not get a non-zero immediate (and 3 more) (3024b12f2c, Jin Ma)
• Revert "[PATCH 1/2] RISC-V:Add intrinsic support for the CMOs extensions" (3f641a8f1d, Jeff Law)
• [PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_ONLY for XTheadVector. (b9493e98da, Jin Ma)
• [PR target/114442] Add reservations for all insn types to xiangshan-nanhu model (64a162d556, Jeff Law)
• RISC-V: Add sifive_vector.h (43a6001ff5, Kito Cheng)
• [PATCH] riscv: add mising masking in lrsc expander (PR118137) (013e66ea95, Andreas Schwab)
• [RISC-V][PR target/118170] Add HF div/sqrt reservation (d6f1961e68, Anton Blanchard)
• RISC-V: vector absolute difference expander [PR117722] (b755c151fd, Vineet Gupta)
• [PR target/116256] Fix latent regression in pattern to associate arithmetic to simplify constants (59e5d086a3, Jeff Law)
• RISC-V: Improve bitwise and ashift reassociation for single-bit immediate without zbs [PR 115921] (107d5d6825, Xi Ruoyao)
• RISC-V: Update Xsfvfnrclip implementation. (030aaea78c, Jiawei)
• RISC-V: Fix incorrect code gen for scalar signed SAT_TRUNC [PR117688] (and 4 more) (5a48079c15, Pan Li)
• RISC-V: Remove zba check in bitwise and ashift reassociation [PR 115921] (a9ebf24906, Xi Ruoyao)
• RISC-V: Remove unused variable in riscv_file_end function. (and 4 more) (3c34cea666, Monk Chiang)
• RISC-V: Refine registered_functions list for rvv overloaded intrinsics. (00b77db92e, xuli)

Notable Changes

• [RISCV][VLOPT] Add vector single width floating point add subtract instructions to isSupportedInstr (c036a9a2c2, Michael Maitland)
• [RISCV][VLOPT] Add Vector Single-Width Averaging Add and Subtract to isSupportedInstr (#122351) (04e54cc19f, Michael Maitland)
• [RISCV][VLOPT] Add vector widening floating point add subtract instructions to isSupportedInstr (8beb9d393d, Michael Maitland)
• [RISCV][VLOPT] Add Vector Floating-Point Compare Instructions to getSupportedInstr (5f70fea79f, Michael Maitland)
• [RISCV][VLOPT] Add vector fp-conversion instruction to isSupportedInstr (#122033) (e93181bf13, Michael Maitland)
• [RISCV][VLOPT] Add vector fp min/max instructions to isSupportedInstr (#124196) (f402e06e7d, Michael Maitland)
• [RISCV] Fold vp.store(vp.reverse(VAL), ADDR, MASK) -> vp.strided.store(VAL, NEW_ADDR, -1, MASK) (#123123) (0c6e03eea0, Craig Topper)
• [RISCV][VLOPT] Add support for checkUsers when UserMI is a Single-Width Integer Reduction (#120345) (142787d368, Michael Maitland)
• [RISCV] Add stack clash vector support (#119458) (6f53886a9a, Raphael Moreira Zinsly)
• [RISCV][VLOPT] Add floating point widening and narrowing bf16 convert support (#122353) (e44f03dd4e, Michael Maitland)
• [RISCV][VLOPT] Add strided, unit strided, and indexed loads to isSupported (#121705) (36e4176f1d, Michael Maitland)
• [RISCV][VLOPT] Add floating point multiply divide instructions to getSupportedInstr (a484fa1d0a, Michael Maitland)
• [RISCV] Add Qualcomm uC Xqcicli (Conditional Load Immediate) extension (#121292) (532a2691bc, Sudharsan Veeravalli)
• [RISCV][VLOPT] Add vmv.x.s and vfmv.f.s to isVectorOpUsedAsScalarOp (#121588) (8b577043b1, Michael Maitland)
• [RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (#123881) (163935a48d, quic_hchandel)

Notable Changes

• elf: Remove the remaining uses of GET_ADDR_OFFSET (cc74583f23, Florian Weimer)
• Add missing include guards to (4a9a8a5098, Florian Weimer)
• Move to kernel-independent sysdeps directories (7a3e2e877a, Florian Weimer)
• Update copyright dates with scripts/update-copyrights (2642002380, Paul Eggert)
• riscv: Update nofpu libm test ulps (274f73978c, Darius Rad)
• RISC-V: Regenerate ULPs (d4b16e22e7, Aurelien Jarno)

Notable Changes

• RISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR. (b4681c2e8a, Monk Chiang)
• RISC-V: Use t2 for tail if Zicfilp enabled (1c618df713, Kito Cheng)
• RISC-V: PR32499, Fix PR18841 segfault caused by ifunc relocation ordering (and 3 more) (a223bdd674, Nelson Chu)
• Update year range in copyright notice of binutils files (e8e7cf2abe, Alan Modra)
• RISC-V: Eliminate redundant instruction macro (a61beb42b0, Xiao Zeng)
• RISC-V: Fix display of partial instructions (6a04e82307, Charlie Jenkins)
• sec->alloced and freeing section contents (cb6326b5ce, Alan Modra)
• gas HANDLE_ALIGN and frag_alloc (b477fdd746, Alan Modra)
• gas tc_gen_reloc memory leaks (3fb6f5457e, Alan Modra)

Notable Changes

• gdb/riscv: Add command to switch between numeric & abi register names (2047479c10, Ciaran Woodward)
• gdb: add "unwinder class" to frame unwinders (ce36ef63aa, Guinevere Larsen)
• [gdb/tdep] Fix gdb.cp/non-trivial-retval.exp on riscv64-linux (84067a55fc, Tom de Vries)
• gdb: Migrate frame unwinders to use C++ classes (1239e7cf37, Guinevere Larsen)

Notable Changes

• riscv: cpu: k230: Add support for Canaan Kendryte K230 SoC (78d9ce3e36, Junhui Liu)
• riscv: dts: canaan: Add basic device tree for K230 CanMV board (a1135b7526, Junhui Liu)
• riscv: Enhance extension probing (ab15e20ea9, Mayuresh Chitale)
• riscv: dts: starfive: split out visionfive2 target specific configuration (9c4d760637, E Shattow)
• efi_loader: correct SizeOfCode, SizeOfInitializedData (216459d2cf, Heinrich Schuchardt)
• efi_loader: use INCLUDE in EFI linker scripts (6a628c1503, Heinrich Schuchardt)
• riscv: Fallback to riscv,isa (4492c8db60, Mayuresh Chitale)

Notable Changes

• Mark all NuttX targets as tier 3 target and support the standard library (ebf53630db, Huang Qi)

Notable Changes

• Add Linux SPI device SWD adapter support (83e0293f7b, Richard Pasek)
• flash/stm32l4x: add STM32C071xx support (250ab1008b, David (Pololu))
• flash/nor: add DesignWare SPI controller driver (eb6f2745b7, Sergey Matsievskiy)
• helper: list: rename macro clashing with sys/queue.h (26f2df80c3, Antonio Borneo)

Notable Changes

• Optimized the gemm_tcopy_8_rvv to be compatible with the vlens 128 and 256. (ef7f54b357, tingbo.liao)
• Optimize the omatcopy_cn and zomatcopy_cn kernels with RVV 1.0 intrinsic. (0a5dbf13d3, tingbo.liao)
• Further rearranged the rotm kernel for the different architectures. (3c8df6358f, tingbo.liao)
• Update Makefile.riscv64 (05dce05c24, Felix LeClair)

Notable Changes

• dt-bindings: riscv: Add xtheadvector ISA extension description (e576b7cb81, Charlie Jenkins)
• dt-bindings: cpus: add a thead vlen register length property (bf6279b38a, Charlie Jenkins)
• dt-bindings: riscv: Add SpacemiT X60 compatibles (16c9147e6a, Yangyu Chen)
• dt-bindings: riscv: add SpacemiT K1 bindings (244fe889b9, Yangyu Chen)