RISC-V Software News

February 2025 — Upstream Open Source Activity

The Big Picture

February brought 289 commits across 11 projects in the RISC-V stack. LLVM (RISC-V) led with 155 commits (53%). Also active: Linux Kernel (RISC-V) (41), OpenSBI (34), QEMU (RISC-V) (16). Extension support work touched Zicond. Virtualisation saw 8 KVM-related patches. Most-discussed mailing list thread: "RISC-V: Fix abort when displaying .dword" (Binutils (RISC-V), 8 replies).

RISC-V International

The spec repos saw 38 commits this month, led by ISA Manual with 20 commits.

Spec Repository Activity

RepositoryCommitsContributors
ISA Manual 20 9
SBI Spec 11 5
Debug Spec 5 3
Profiles 1 1
ELF psABI 1 1

Linux Kernel (RISC-V)

41
Commits
22
Contributors
477
Lines Added
361
Lines Removed

Linux Kernel (RISC-V) had a solid month with 41 commits from 22 contributors. Leading the charge was Andrew Jones with 6 commits. New feature work included 12 commits: "mm: hugetlb: Add huge page size param to huge_ptep_get_and_clear()"; "riscv: sophgo: dts: Add msi controller for SG2042". Platform and DT work accounted for 12 commits. Virtualisation work accounted for 8 patches, continuing to mature RISC-V KVM support. Bug fixes accounted for 8 commits (19%).

12 New features & support 12 Device tree / platform support 8 KVM / Virtualisation 8 Bug fixes 7 Interrupt controllers (AIA/APLIC/PLIC) 1 Vector extension (RVV) 1 ISA extensions 1 Cleanup & refactoring

Notable Changes

  • irqchip/riscv-aplic: Add support for hart indexes (b93afe8a3a, Vladimir Kondratiev)
  • riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port (and 2 more) (38818f7c9c, E Shattow)
  • riscv/atomic: Do proper sign extension also for unsigned in arch_cmpxchg (1898300abf, Andreas Schwab)
  • KVM: Drop kvm_arch_sync_events() now that all implementations are nops (b2aba529bf, Sean Christopherson)
  • mm: hugetlb: Add huge page size param to huge_ptep_get_and_clear() (02410ac72a, Ryan Roberts)
  • riscv: dts: microchip: update pcie reg properties to new format (9b181f4a95, Conor Dooley)
  • riscv: sophgo: dts: Add msi controller for SG2042 (and 3 more) (0edaa4593e, Chen Wang)
  • riscv: dts: spacemit: Add Milk-V Jupiter board device tree (5b90a3d609, Javier Martinez Canillas)
  • riscv: vdso: Switch to generic storage implementation (46fe55b204, Thomas Weißschuh)
  • riscv: dts: starfive: fml13v01: enable pcie1 (57b5369f36, Sandie Cao)
  • pinctrl: spacemit: enable config option (7ff4faba63, Yixun Lan)
  • irqchip/riscv-imsic: Special handling for non-atomic device MSI update (and 3 more) (896f8e436f, Anup Patel)
  • riscv: cacheinfo: Use of_property_present() for non-boolean properties (fb8179ce29, Rob Herring)
  • lib/crc32: don't bother with pure and const function attributes (bc2736fe7e, Eric Biggers)
  • mm/memremap: Pass down MEMREMAP_* flags to arch_memremap_wb() (a9ebcb8813, Kirill A. Shutemov)

Top Contributors

AuthorCommits
Andrew Jones6
Anup Patel5
Chen Wang4
E Shattow3
Thomas Weißschuh2
Conor Dooley2
Yong-Xuan Wang2
Andreas Schwab2
Eric Biggers2
Ryan Roberts1

OpenSBI

34
Commits
10
Contributors
905
Lines Added
729
Lines Removed

OpenSBI kept moving with 34 commits from 10 contributors. Top contributor: Anup Patel with 14 commits. The interrupt subsystem got 12 patches of attention this month. Board and device tree support got 7 commits. Bug fixes accounted for 4 commits (11%).

12 Interrupt controllers (AIA/APLIC/PLIC) 7 Device tree / platform support 5 New features & support 4 Bug fixes 2 ISA extensions

Notable Changes

  • lib: utils: Add MPXY RPMI mailbox driver for System MSI service group (and 7 more) (61abd975f2, Anup Patel)
  • platform: generic: thead: add Sophgo SG2044 (a7f3c159a0, Inochi Amaoto)
  • include: sbi: Add SBI_ERR_DENIED_LOCKED (b91ab20cd2, Clément Léger)
  • lib: sbi: fwft: Return SBI_ERR_DENIED_LOCKED when setting a locked feature (and 2 more) (1ad1991244, Clément Léger)
  • README: Remove comment about boolin toolchains being 64-bit only (and 2 more) (fe11dee7ea, Joel Stanley)
  • lib: utils/irqchip: Match against more specific compatible strings first (6019259dfb, Alex Studer)
  • include: sbi_utils: Update RPMI service group IDs and BASE service group (b05e2a1956, Anup Patel)
  • lib: utils/fdt: Allocate fdt_pmu_evt_select on the heap (and 2 more) (a2c172f526, Samuel Holland)
  • lib: utils: Make the enforce permission bit configurable from DT (3f25380d85, Chao Du)
  • include: sbi_utils: Include mailbox.h in rpmi_mailbox.h header (f8272946da, Anup Patel)
  • firmware: fw_base.S: Fix comments for _wait_for_boot_hart (82da072eb4, Xiang W)
  • include: sbi: Align SBI trap registers to a nice boundary (4f12f8b02f, Raj Vishwanathan)
  • lib: utils: Initialize miscellaneous drivers in one pass (434add551c, Samuel Holland)
  • lib: utils/irqchip: Use fdt_driver for initialization (9e1a1518d4, Samuel Holland)
  • lib: sbi: Fix non-root domain startup (and 3 more) (1f64fef919, Anup Patel)

Top Contributors

AuthorCommits
Anup Patel14
Samuel Holland6
Clément Léger4
Joel Stanley3
Raj Vishwanathan2
Alex Studer1
Inochi Amaoto1
Xiang W1
Chao Du1
Huang Borong1

QEMU (RISC-V)

16
Commits
7
Contributors
35
Lines Added
50
Lines Removed

QEMU (RISC-V) kept moving with 16 commits from 7 contributors. Philippe Mathieu-Daudé was the most active contributor with 8 commits.

3 Cleanup & refactoring 1 Bug fixes

Notable Changes

  • hw/riscv/opentitan: Include missing 'exec/address-spaces.h' header (bb741c4f40, Philippe Mathieu-Daudé)
  • tests/qtest: rename qtest_send_prefix and roll-up into qtest_send (31ef3c333d, Alex Bennée)
  • target/riscv: Fix minor whitespace issue in riscv_cpu_properties (0f35d854d2, Rob Bradford)
  • hw/char/xilinx_uartlite: Make device endianness configurable (8a8c92c8af, Philippe Mathieu-Daudé)
  • hw/riscv: Remove all invalid uses of auto_create_sdcard=true (b5d5edc1d9, Philippe Mathieu-Daudé)
  • hw/timer/xilinx_timer: Make device endianness configurable (df1f35ab67, Philippe Mathieu-Daudé)
  • hw/net/xilinx_ethlite: Make device endianness configurable (644276db5d, Philippe Mathieu-Daudé)
  • hw/intc/xilinx_intc: Make device endianness configurable (2cdf693b19, Philippe Mathieu-Daudé)
  • hw/boards: Explicit no_sdcard=false as ON_OFF_AUTO_OFF (8a2f1f921c, Philippe Mathieu-Daudé)
  • hw: Centralize handling of -machine dumpdtb option (8fd2518ef2, Peter Maydell)
  • target/*: Remove TARGET_LONG_BITS from cpu-param.h (175646f641, Richard Henderson)
  • hw/boards: Rename no_sdcard -> auto_create_sdcard (cdc8d7cada, Philippe Mathieu-Daudé)
  • qapi: Move include/qapi/qmp/ to include/qobject/ (407bc4bf90, Daniel P. Berrangé)
  • target/riscv: move 128-bit check to TCG realize (aeb7969cba, Paolo Bonzini)
  • target/riscv: remove unused macro DEFINE_CPU (4044f46978, Paolo Bonzini)

Top Contributors

AuthorCommits
Philippe Mathieu-Daudé8
Paolo Bonzini2
Richard Henderson2
Peter Maydell1
Rob Bradford1
Daniel P. Berrangé1
Alex Bennée1

GCC (RISC-V)

15
Commits
9
Contributors
236
Lines Added
72
Lines Removed

GCC (RISC-V) saw moderate activity with 15 commits from 9 contributors. Leading the charge was Robin Dapp with 4 commits. Bug fixes accounted for 7 commits (46%). Vector extension support moved forward with 4 commits.

7 Bug fixes 4 Vector extension (RVV) 3 ISA extensions 1 Compiler backend / code generation

Notable Changes

  • RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets (580f571be6, Jin Ma)
  • RISC-V: Fix bug for expand_const_vector interleave [PR118931] (and 2 more) (e7287cbbb2, Pan Li)
  • RISC-V: Bugfix ICE for RVV intrinisc when using no-extension parameters (25a103feb3, Jin Ma)
  • [RISC-V][PR target/118146] Fix ICE for unsupported modes (9576353454, Jeff Law)
  • RISC-V: Vector pesudoinsns with x0 operand to use imm 0 (3880271e94, Vineet Gupta)
  • RISC-V: Include pattern stmts for dynamic LMUL computation [PR114516]. (and 3 more) (6be1b9e94d, Robin Dapp)
  • [PATCH] RISC-V: Move UNSPEC_SSP_SET and UNSPEC_SSP_TEST to correct enum (ba58506478, Craig Blackmore)
  • [PR target/118248] Avoid bogus alloca call in RISC-V backend (68e74199c6, Jakub Jelinek)
  • RISC-V: Fix .cfi_offset directive when push/pop in zcmp (4dcd3c7749, Lino Hsing-Yu Peng)
  • RISC-V: Drop __riscv_vendor_feature_bits (2605daa6b8, Yangyu Chen)

Top Contributors

AuthorCommits
Robin Dapp4
Pan Li3
Jin Ma2
Lino Hsing-Yu Peng1
Jakub Jelinek1
Vineet Gupta1
Yangyu Chen1
Jeff Law1
Craig Blackmore1

LLVM (RISC-V)

155
Commits
36
Contributors
98610
Lines Added
69074
Lines Removed

Plenty of action in LLVM (RISC-V) this month: 155 commits from 36 contributors. That's +98,610/-69,074 lines of churn. Top contributor: Craig Topper with 41 commits. New feature work included 34 commits: "[RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130)"; "[RISCV][TTI] Add shuffle costing for masked slide lowering (#128537)". The compiler backend saw heavy activity with 24 commits touching code generation. Work on Zicond accounted for 14 commits.

38 Cleanup & refactoring 34 New features & support 24 Compiler backend / code generation 14 ISA extensions 13 Vector extension (RVV) 11 Bug fixes

Notable Changes

  • [RISCV] Xqcia 0.4 The spec was recently updated, this changes the name in the TD files associated and increments the Extension number in the clang driver. This is mostly a MC change as there is no other generated code for these instructions yet. (aace6a2f9d, Luke Quinn)
  • [RISCV][VLOPT] Add support for Vector Fixed-Point Arithmetic Instructions (#126483) (36530414e3, Luke Lau)
  • [RISCV] Add policy operand to masked vector compare pseudos. Remove ForceTailAgnostic. NFC (#127575) (9516f44f6b, Craig Topper)
  • [RISCV][VLOPT] Add support for Single-Width Floating-Point Fused Multiply-Add Instructions (#125652) (19a41358ff, Luke Lau)
  • [clang][RISCV] Introduce preprocessor macro when Zicfiss-based shadow stack is enabled (#127592) (2fdb26da61, Ming-Yi Lai)
  • [RISCV][VLOPT] Add support for Widening Floating-Point Fused Multiply-Add Instructions (#126485) (771f6b9f43, Luke Lau)
  • [RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130) (81387754c3, Craig Topper)
  • [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706) (538b898a83, quic_hchandel)
  • [RISCV][VLOPT] Add vfsqrt/vfrsqrt7 instruction to isSupportInstr (#127462) (fb394451ca, LiqinWeng)
  • [RISCV] The test for vp.reduce.fminimum/fmaximum with fixed-length should stay in fixed-vectors-reduction-fp-vp.ll. (NFC) (a565f9eb29, Jim Lin)
  • [RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (#129172) (0b5bb12534, Craig Topper)
  • [RISCV][MC] Add assembler support for XRivosVisni (#128773) (8039f8e139, Philip Reames)
  • [IR][RISCV] Add llvm.vector.(de)interleave3/5/7 (#124825) (5a1e16f6de, Min-Yih Hsu)
  • Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)" (26e375046d, Craig Topper)
  • [RISCV] Check isFixedLengthVector before calling getVectorNumElements in getSingleShuffleSrc. (#125455) (7c5100d36d, Craig Topper)

Top Contributors

AuthorCommits
Craig Topper41
Philip Reames26
Luke Lau17
Sam Elliott10
Min-Yih Hsu7
Pengcheng Wang5
Mikhail R. Gadelha5
Sudharsan Veeravalli4
Piotr Fusik4
Chandler Carruth3

glibc (RISC-V)

8
Commits
2
Contributors
11
Lines Added
41
Lines Removed

glibc (RISC-V) saw lighter activity with 8 commits from 2 contributors. Most of the work came from Adhemerval Zanella (7 of 8 commits, 87%).

1 Bug fixes

Notable Changes

  • RISC-V: Fix IFUNC resolver cannot access gp pointer (3fd2ff7685, Yangyu Chen)
  • math: Use tanpif from CORE-MATH (and 6 more) (8f170dc819, Adhemerval Zanella)

Top Contributors

AuthorCommits
Adhemerval Zanella7
Yangyu Chen1

Notable Discussions

Binutils (RISC-V)

7
Commits
6
Contributors
214
Lines Added
183
Lines Removed

Binutils (RISC-V) saw lighter activity with 7 commits from 6 contributors.

2 New features & support 1 Security & memory safety fixes 1 ISA extensions 1 Bug fixes

Notable Changes

  • RISC-V: Add .bfloat16 directive (83c30fcc4d, Kito Cheng)
  • RISC-V: Move all global static target stuff into private data for disassembler. (3f61a38b5e, Nelson Chu)
  • RISC-V: Add OP_VE for .insn (d7657a4cee, Kito Cheng)
  • RISC-V: Fix abort when displaying data and partial instructions (227a52fbbd, Charlie Jenkins)
  • RISC-V: Make SSAMOSWAP.W available for rv64 (052d07f84b, Hau Hsu)
  • RISC-V: use is_whitespace() (49343ef904, Jan Beulich)
  • riscv disassembler leak (3a69ff93b5, Alan Modra)

Top Contributors

AuthorCommits
Kito Cheng2
Charlie Jenkins1
Alan Modra1
Hau Hsu1
Nelson Chu1
Jan Beulich1

Notable Discussions

U-Boot (RISC-V)

8
Commits
5
Contributors
90
Lines Added
56
Lines Removed

A quieter month for U-Boot (RISC-V), with 8 commits from 5 contributors.

2 New features & support 1 Device tree / platform support

Notable Changes

  • riscv: add a generic implementation for cleanup_before_linux() (f88e3b7739, Yao Zi)
  • riscv: Add CONFIG_SPL_OPTEE_LOAD_ADDR (99654e1b96, Yu-Chien Peter Lin)
  • board: starfive: Update the maintainer file for VisionFive 2 board (c6337c91e5, Hal Feng)
  • riscv: cpu: generic: fallback to generic cleanup_before_linux() (334980f4cf, Yao Zi)
  • riscv: cpu: jh7110: fallback to generic cleanup_before_linux() (faf237d1b4, Yao Zi)
  • riscv: spacemit: k1: probe dram size during boot phase. (3691fbccfc, Huan Zhou)
  • riscv: AVAILABLE_HARTS is not compatible with XIP (490be9de22, Heinrich Schuchardt)
  • riscv: dts: binman.dtsi: Include OP-TEE OS image (47d90f6bd3, Yu-Chien Peter Lin)

Top Contributors

AuthorCommits
Yao Zi3
Yu-Chien Peter Lin2
Hal Feng1
Heinrich Schuchardt1
Huan Zhou1

Rust (RISC-V)

3
Commits
3
Contributors
111
Lines Added
85
Lines Removed

A light month for Rust (RISC-V) with 3 commits from 3 contributors.

Notable Changes

  • Sync Fuchsia target spec with clang Fuchsia driver (746b0f6f1d, Erick Tryzelaar)
  • rustc_target: import TargetMetadata (b660382f12, Ken Matsui)
  • tests: use minicore more (92eb4450fa, David Wood)

Top Contributors

AuthorCommits
David Wood1
Erick Tryzelaar1
Ken Matsui1

OpenOCD (RISC-V)

1
Commits
1
Contributors
26
Lines Added
27
Lines Removed

Just a single commit landed in OpenOCD (RISC-V) this month.

Notable Changes

  • target: Use 'bool' data type in target_{step,resume} (297844cf46, Marc Schink)

Top Contributors

AuthorCommits
Marc Schink1

Linux Kernel Docs & DT (RISC-V)

1
Commits
1
Contributors
1
Lines Added
0
Lines Removed

Linux Kernel Docs & DT (RISC-V) had exactly one commit this month.

1 New features & support 1 Device tree / platform support

Notable Changes

  • dt-bindings: riscv: spacemit: Add Milk-V Jupiter board compatible (8c8d2a19a3, Javier Martinez Canillas)

Top Contributors

AuthorCommits
Javier Martinez Canillas1