RISC-V Software News

Spec Repository Activity

Notable Changes

• riscv/crc32: reimplement the CRC32 functions using new template (72acff5f81, Eric Biggers)
• riscv: add ISA extension parsing for bfloat16 ISA extension (e186c28dda, Inochi Amaoto)
• RISC-V: add f & d extension validation checks (and 4 more) (12e7fbb6a8, Conor Dooley)
• riscv/crc: add "template" for Zbc optimized CRC functions (bbe2610bc5, Eric Biggers)
• riscv/crc-t10dif: add Zbc optimized CRC-T10DIF function (8bf3e17898, Eric Biggers)
• riscv: add parsing for Zaamo and Zalrsc extensions (35173b666a, Clément Léger)
• riscv/crc64: add Zbc optimized CRC64 functions (511484fa88, Eric Biggers)
• riscv: Add runtime constant support (a44fb57221, Charlie Jenkins)
• riscv: ftrace: Add parentheses in macro definitions of make_call_t0 and make_call_ra (5f1a58ed91, Juhan Jin)
• kbuild: Introduce Kconfig symbol for linking vmlinux with relocations (9b400d1725, Ard Biesheuvel)
• RISC-V: KVM: Optimize comments in kvm_riscv_vcpu_isa_disable_allowed (b3f263a98d, Chao Du)
• riscv: Fix missing __free_pages() in check_vector_unaligned_access() (33981b1c4e, Alexandre Ghiti)
• riscv: Add parameter for skipping access speed tests (and 6 more) (aecb09e091, Andrew Jones)
• riscv: Simplify base extension checks and direct boolean return (7f238b1266, Chin Yik Ming)
• riscv: Fix the __riscv_copy_vec_words_unaligned implementation (475afa39b1, Tingbo Liao)

Notable Changes

• lib: sbi: sse: Add support for SSTATUS.SDT (and 6 more) (3ac49712e3, Clément Léger)
• lib: utils/serial: Add PXA UARTs support (8fe835303c, Junhui Liu)
• lib: sbi_scratch: Add sbi_hart_count() and for_each_hartindex() (and 2 more) (757f7acafd, Samuel Holland)
• lib: tests: add bitwise operations unit tests (3e6bd14246, Dongdong Zhang)
• lib: add tests for sbi_ecall functionality (0b78665a6c, Akshay Behl)
• Revert "lib: utils/irqchip: Match against more specific compatible strings first" (98c0a3860a, Samuel Holland)
• scripts: Fix firmware binaries compilation in create-binary-archive.sh (8573a9b858, Anup Patel)
• lib: sbi: Return SBI_EALREADY error code if SSE event is present (b2e8e6986d, Himanshu Chauhan)
• lib: utils: Make sure that hartid and the scratch are aligned (321ca8063b, Raj Vishwanathan)
• lib: sbi: Fix potential garbage data in string copy functions (56341e95ae, Dongdong Zhang)
• lib: sbi: Avoid GOT indirection for global symbol references (86c01a73ff, Samuel Holland)
• lib: sbi: Use sbi_hart_count() and sbi_for_each_hartindex() (949c83a799, Samuel Holland)
• lib: utils/fdt: Respect compatible string fallback priority (0ffe265fd9, Samuel Holland)
• lib: Emit lr and sc instructions based on -march flags (995f226f3f, Chao-ying Fu)

Notable Changes

• target/riscv: Add support to access ctrsource, ctrtarget, ctrdata regs. (and 5 more) (8b65852196, Rajnesh Kanwal)
• optimize the memory probing for vector fault-only-first loads. (17288e38be, Paolo Savini)
• target/riscv/kvm: Add some exts support (1c17df6fc4, Quan Zhou)
• target/riscv: rvv: Fix unexpected behavior of vector reduction instructions when vl is 0 (ffd455963f, Max Chou)
• target/riscv: fix handling of nop for vstart >= vl in some vector instruction (4e9e2478df, Chao Liu)
• target/riscv: Add check for 16-bit aligned PC for different priv versions. (ffe4db11f8, Yu-Ming Chang)
• target/riscv: machine: Add Control Transfer Record state description (bda6522e3f, Rajnesh Kanwal)
• hw/riscv/riscv-iommu: add hpm events mmio write (and 5 more) (4faa3e6f90, Tomasz Jeznach)
• target/riscv/cpu: remove unneeded !kvm_enabled() check (1a65210876, Daniel Henrique Barboza)
• target/riscv/kvm: add missing KVM CSRs (and 2 more) (4db19d5b21, Daniel Henrique Barboza)
• hw/riscv/riscv-iommu.c: add RISCV_IOMMU_CAP_HPM cap (3b1d07b627, Tomasz Jeznach)
• Revert "target/riscv/kvm: add missing KVM CSRs" (897c68fb79, Daniel Henrique Barboza)
• target/riscv: add RVA23S64 profile (and 6 more) (c91f74b91d, Daniel Henrique Barboza)
• hw/riscv/riscv-iommu.h: add missing headers (5bdbbacb8c, Daniel Henrique Barboza)
• hw/riscv/virt: Add serial alias in DTB (f73456781b, Vasilis Liaskovitis)

Notable Changes

• RISC-V: Mask values before initializing bitmask vector [PR119114]. (and 2 more) (b58a0af4e2, Robin Dapp)
• [RISC-V][PR target/118934] Fix ICE in RISC-V long branch support (67e824c249, Jeff Law)
• [RISC-V][PR target/116256][V4] Fix minor code quality regression in reassociated arithmetic (9d68a2a673, Jeff Law)
• [RISC-V] Fix unreported code quality regression with single bit manipulations (d9a8ec7fe0, Jeff Law)
• RISC-V: disable the abd expander for gcc-15 release [PR119224] (cb6070c79d, Vineet Gupta)
• [RISC-V] Fix another unreported code quality regression (e9888795b8, Jeff Law)

Notable Changes

• [RISCV] Enable scalable loop vectorization for fmax/fmin reductions with f16/bf16 type for zvfhmin/zvfbfmin (#129629) (03505a004f, Jim Lin)
• [RISCV] Add vector hasAndNot to enable optimizations (#132438) (96925fa84c, Piotr Fusik)
• [RISCV] Add missing space to optimized-nf*-segment-load-store description. NFC (#132531) (fb44c54d65, Craig Topper)
• Recommit "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)" (#132520) (e7107973b8, Sudharsan Veeravalli)
• [RISCV] Add Qualcomm uC Xqciio (External Input Output) extension (#132721) (edef028029, quic_hchandel)
• Revert "[RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184)" (fe7776eab8, Kazu Hirata)
• [MC] Rework AVR #121498 to not add extra argument to shouldForceRelocation (8a1b4d0ed2, Fangrui Song)
• [RISCV] Add Qualcomm uC Xqcili (load large immediates) extension (#130012) (e61859f14d, u4f3)
• [RISCV] Initial codegen support for the XRivosVizip extension (#131933) (f8ee58a3cb, Philip Reames)
• [RISCV] Add coverage for vector stack slot coloring and dead copy elim (e86d627a8b, Philip Reames)
• [RISCV] Add Qualcomm uC Xqcisim (Simulation Hint) extension (#128833) (467e5a1d41, Sudharsan Veeravalli)
• [RISCV] Add Qualcomm uC Xqcibi (Branch Immediate) extension (#130779) (036c6cb37c, quic_hchandel)
• [RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504) (6e7e46cafe, quic_hchandel)
• [RISCV] Add Qualcomm uC Xqcisync (Sync Delay) extension (#132184) (3840f787a2, quic_hchandel)
• [RISCV] Add Qualcomm uC Xqcilb (Long Branch) extension (#131996) (0744d4926a, quic_hchandel)

Notable Changes

• Add _FORTIFY_SOURCE support for inet_pton (e3a6e85d67, Aaron Merey)
• Add _FORTIFY_SOURCE support for inet_ntop (090dfa40a5, Frédéric Bérat)
• Linux: Add the pthread_gettid_np function (bug 27880) (74d463c50b, Florian Weimer)
• Implement C23 rsqrt (77261698b4, Joseph Myers)
• Implement C23 pown (75ad83f564, Joseph Myers)
• Implement C23 powr (409668f6e8, Joseph Myers)
• math: Refactor how to use libm-test-ulps (3e8814903c, Adhemerval Zanella)
• Update syscall lists for Linux 6.13 (eea6f1e079, Joseph Myers)

Notable Changes

• RISC-V: Add extension XTheadVdot for T-Head VECTOR vendor extension [1] (66b81b40dc, Jin Ma)
• RISC-V: Support ssqosid extension with version 1.0. (56a0188548, Kito Cheng)
• RISC-V: Support pointer masking extension 1.0 (7b2a5f7183, Jerry Zhang Jian)
• RISC-V: add Smrnmi 1.0 instruction support (a7ecc1ba97, Jerry Zhang Jian)
• RISC-V: Don't show support for 1.9.1 priv spec (0d1f436268, Marek Pikuła)
• RISC-V: Avoid parsing arch string repeatedly for dis-assembler (and 5 more) (e4c9f0e6c3, Nelson Chu)
• RISC-V: Re-define mapping symbol $x to the file elf architecture attribute (ade87b8e62, Andrew Oates)
• RISC-V: Ssnpm, smnpm and smmpm imply zicsr. (bc965121b5, Dongyan Chen)
• RISC-V: use is_end_of_stmt() (64ac402023, Jan Beulich)

Notable Changes

• boot: arm: riscv: sandbox: Add a format for the booti file (098407e673, Simon Glass)
• riscv: dts: k1: add reset controller node in device tree (d5b621d8b5, Huan Zhou)
• treewide: Add a function to change page permissions (ec1c6cfb1c, Ilias Apalodimas)
• spl: Add an SPL_HAVE_INIT_STACK option (d6a53f523a, Simon Glass)
• Add reset config options for k1 (9c40d92305, Huan Zhou)
• board: starfive: Remove compatible boards Milk-V Mars CM and Mars CM Lite (870c4d105a, E Shattow)
• spl: starfive: visionfive2: Disable USB overcurrent pin by default. (05aa34cef9, Minda Chen)
• riscv: dts: starfive: remove duplicate itb entries (and 2 more) (29dbfbeba4, Heinrich Schuchardt)
• arm: riscv: efi: Export _start symbol from crt0_*_efi stubs (214a87757a, Sam Edwards)
• usb: gadget: Remove final remnants of CONFIG_USB_DEVICE (7f061aba9a, Tom Rini)
• riscv: dts: spacemit: Update UART compatible for k1 (f1ba590136, Junhui Liu)
• board: starfive: spl: strip off 'starfive/' prefix (3962acf0a4, Heinrich Schuchardt)
• spl: Use CONFIG_VAL() to obtain the SPL stack (ffa98c08e8, Simon Glass)
• riscv: dts: cv18xx: Drop unused dummy clocks (a44f389263, Yao Zi)
• common: clean up setjmp.h (7082c9e656, Heinrich Schuchardt)

Notable Changes

• replace config.toml to bootstrap.toml in src:doc:rustc (85e9da8e60, bit-aloo)
• Fix RISC-V VxWorks LLVM target triples (0434013a6e, Mads Marquart)
• Fix some typos (4febd273e5, fuyangpengqi)

Notable Changes

• flash/nor: Add basic support for TI's MSPM0L/G family (8a6f89ca17, Nishanth Menon)
• tcl/target: Add support for TI MSPM0 (c81cb4aa2d, Nishanth Menon)
• doc: drop mention of not implemented SPI transport (e4a51b3235, Antonio Borneo)
• adapter: drop command 'adapter transports' (6beb6280af, Antonio Borneo)

Notable Changes

• dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description (a65e0f67da, Clément Léger)
• dt-bindings: riscv: add bfloat16 ISA extension description (35bc188373, Inochi Amaoto)
• dt-bindings: riscv: document vector crypto requirements (and 2 more) (a0d8572057, Conor Dooley)