RISC-V Software News

Spec Repository Activity

Notable Changes

• riscv: defconfig: spacemit: enable gpio support for K1 SoC (8ec8b25dde, Yixun Lan)
• riscv: defconfig: spacemit: enable clock controller driver for SpacemiT K1 (60c6d37972, Haylen Chu)
• riscv: Make sure toolchain supports zba before using zba instructions (8a2f20ac8e, Alexandre Ghiti)
• riscv: dts: thead: Introduce power domain nodes with aon firmware (2bae46e3de, Michal Wilczynski)
• riscv: uprobes: Add missing fence.i after building the XOL buffer (7d1d19a11c, Björn Töpel)
• RISC-V: vDSO: Wire up getrandom() vDSO implementation (89079520ce, Xi Ruoyao)
• riscv: misaligned: Add handling for ZCB instructions (7b30b1b04e, Nylon Chen)
• riscv: Add norvc after .option arch in runtime const (6ee928185a, Charlie Jenkins)
• riscv: dts: thead: Introduce reset controller node (1b136de08b, Michal Wilczynski)
• riscv: Enable PM_GENERIC_DOMAINS for T-Head SoCs (54fe9380a5, Michal Wilczynski)
• riscv: misaligned: fix sleeping function called during misaligned access handling (61a74ad254, Nylon Chen)
• crypto: lib/chacha - remove INTERNAL symbol and selection of CRYPTO (and 4 more) (879f47548b, Eric Biggers)
• riscv: KGDB: Remove ".option norvc/.option rvc" for kgdb_compiled_break (550c2aa787, WangYuli)
• riscv: switch set_icache_stale_mask() to using non-atomic assign_cpu() (e5bf9a4b68, Yury Norov)
• riscv: Fix hugetlb retrieval of number of ptes in case of !present pte (83d78ac677, Alexandre Ghiti)

Notable Changes

• lib: sbi_trap: Add support for vectored interrupts (afa0e3091b, Samuel Holland)
• lib: sbi: Handle length of extension name string exceed buffer size error (d2166a9d40, Jimmy Ho)
• lib: sbi: Enable Control Transfer Records (CTR) Ext using xstateen. (aa40c53ce4, Rajnesh Kanwal)
• docs: pmu_support: fix example typos (5ab908d622, Leo Yu-Chi Liang)
• sbi: Introduce sbi_hartmask_weight (a6e5f8878c, Andrew Jones)
• lib: sbi: Allow programmable counters to monitor cycle/instret events for Andes PMU (0442f1318e, Leo Yu-Chi Liang)
• platform: rzfive: Call andes_pma_setup_regions() only during cold boot (ac2e428c4b, Samuel Holland)
• platform: generic: Initialize overrides with fdt_driver (and 6 more) (1c579675be, Samuel Holland)
• lib: sbi: Set the scratch allocation to alignment to cacheline size (99aabc6b84, Raj Vishwanathan)
• lib: sbi_domain: Reduce memory usage of per-domain hart context (4d0128ec58, Alvin Chang)
• lib: sbi: Remove unnecessary SBI_INIT_LIST_HEAD (and 3 more) (190979b4fc, Xiang W)
• Makefile: Avoid repeated evaluation of shell commands (2142618f12, Samuel Holland)
• lib: sbi_platform: Remove the vendor_ext_check hook (2b09a98701, Samuel Holland)
• lib: sbi_mpxy: Change MPXY state as per-domain data (fda0742e76, Alvin Chang)
• lib: sbi_ipi: Return error for invalid hartids (37eaca4ab3, Andrew Jones)

Notable Changes

• tcg: Convert TARGET_SUPPORTS_MTTCG to TCGCPUOps::mttcg_supported field (a3d40b5eff, Philippe Mathieu-Daudé)
• include/system: Move exec/address-spaces.h to system/address-spaces.h (dfc56946a7, Richard Henderson)
• tcg: Move qemu_tcg_mttcg_enabled() to 'system/tcg.h' (and 3 more) (60b2c2e66b, Philippe Mathieu-Daudé)
• target/riscv: Do not expose rv128 CPU on user mode emulation (8280a8b866, Philippe Mathieu-Daudé)
• target/riscv: Remove ifndef CONFIG_USER_ONLY from cpu_cfg.h (e4610f3809, Richard Henderson)
• target/riscv: Remove AccelCPUClass::cpu_class_init need (f50d0f335a, Philippe Mathieu-Daudé)
• codebase: prepare to remove cpu.h from exec/exec-all.h (2ec0dc245f, Pierrick Bouvier)
• qom: Have class_init() take a const data argument (12d1a768bd, Philippe Mathieu-Daudé)
• cleanup: Drop pointless return at end of function (8a2b516ba2, Markus Armbruster)
• target/riscv: Restrict SoftMMU mmu_index() to TCG (bf8dc33bbc, Philippe Mathieu-Daudé)
• exec/cpu-all: remove this header (and 6 more) (0df783b2fb, Pierrick Bouvier)
• exec: Restrict 'cpu_ldst.h' to accel/tcg/ (42fa9665e5, Philippe Mathieu-Daudé)
• cleanup: Re-run return_directly.cocci (720a0e417e, Markus Armbruster)
• qom: Make InterfaceInfo[] uses const (2cd09e47aa, Philippe Mathieu-Daudé)
• include/exec: Split out watchpoint.h (3e57baa22e, Richard Henderson)

Notable Changes

• RISC-V: Disable unsupported vsext/vzext patterns for XTheadVector. (196b45caca, Jin Ma)
• [PATCH] riscv: Add support for riscv*-gnu (GNU/Hurd on RISC-V) (869f2ab30a, Hakan Candar)
• [PATCH v2] RISC-V: Fixbug for slli + addw + zext.w into sh[123]add + zext.w (dd6ebc0a34, Jin Ma)
• RISC-V: Extract vector stepped for expand_const_vector [NFC] (and 3 more) (ab22b8c630, Pan Li)
• [PATCH] [RISC-V]Support -mcpu for Xuantie cpu (bd8a48500c, Yixuan Chen)
• [PATCH] RISC-V: Do not free a riscv_arch_string when handling target-arch attribute (2d6f1ca17f, 翁愷邑)
• [PATCH] [RISC-V] Tune for removal unnecessary sext in builtin overflows [PR108016] (529a43109f, Alexey Merzlyakov)
• RISC-V: Fix the behavior for multilib-generator with --cmodel=large on rv32 (72dff34bcd, Kito Cheng)
• [riscv] vec_dup immediate constants in pred_broadcast expand [PR118182] (14fa625bcb, Alexandre Oliva)
• [RISC-V][PR target/118410] Improve code generation for some logical ops (874f4c1647, Jeff Law)
• RISC-V: vsetvl: elide abnormal edges from LCM computations [PR119533] (edb4867412, Vineet Gupta)
• RISC-V: Do not lift up vsetvl into non-transparent blocks [PR119547]. (517f7e3f02, Robin Dapp)
• [RISC-V][PR target/119865] Don't free ggc allocated memory (1a64b224fa, Jeff Law)
• RISC-V: Fix register move cost for SIBCALL_REGS/JALR_REGS (102eccaf8e, Zhijin Zeng)
• RISC-V: Fix vec_duplicate[bimode] expander [PR119572]. (716d39f0a2, Robin Dapp)

Notable Changes

• [RISCV] Add codegen tests for `vector.(de)interleave3/5/7` on FP scalable vectors (#137257) (7122d9c562, Min-Yih Hsu)
• Revert "[llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions" (#137657) (7ee0097b48, Jonathan Thackray)
• [RISCV] Add symbol parsing support for Xqcili load large immediate instructions (#134581) (1d2f5ead05, Sudharsan Veeravalli)
• [RISCV] Add symbol parsing support for the Xqcibi branch immediate instructions (#134233) (ae5306f30e, Sudharsan Veeravalli)
• [RISCV] Add new CondCode COND_CV_BEQIMM/COND_CV_BNEIMM for CV immediate branch (#135771) (0439a4eca7, Jim Lin)
• [TableGen][RISCV][AArch64][GISel] Properly implement isAnyExtLoad/isSignExtLoad/isZeroExtLoad for IsAtomic in SelectionDAG. (#137096) (2ca071b1de, Craig Topper)
• [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (#136759) (ba420d8122, Jonathan Thackray)
• [RISCV] Add symbol parsing support for Xqcilb long branch instructions (#135044) (eccd7aa888, Sudharsan Veeravalli)
• [RISCV] Add test for vmv.s.x of an immediate into a zeroinitializer vector. NFC (c132bd6885, Luke Lau)
• [RISCV] Add codegen support for ri.vinsert.v.x and ri.vextract.x.v (#136708) (9062a38d5d, Philip Reames)
• AsmPrinter: Remove ELF's special lowerRelativeReference for unnamed_addr function; use lowerDSOLocalEquivalent in more cases (7117dea043, Fangrui Song)
• [RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110) (6ba1a62a6c, Jim Lin)
• [RISCV] Support vectorizing FMINIMUMNUM and FMAXIMUMNUM (#135727) (e9a34e4236, YunQiang Su)
• [RISCV] Add test for vmv.s.x into a zeroinitializer vector. NFC (ffaaaceaa1, Luke Lau)
• Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR." (#135056) (378ac572ac, zhijian lin)

Notable Changes

• RISC-V: Use builtin for ffs and ffsll while supported extension available (4c966c0780, Julian Zhu)
• stdlib: Implement C2Y uabs, ulabs, ullabs and uimaxabs (5b132ec2b7, Lenard Mollenkopf)

Notable Changes

• RISC-V: Add missing disassembler option `max` (88891208c3, Marek Pikuła)
• RISC-V: Mark fgt.*/fge.* as instruction alias (10ec3d5de0, Kito Cheng)

Notable Changes

• This commit adds record full support for rv64gc instruction set (b9c7eed0c2, Timur)
• Internal TLS support for aarch64, x86_64, riscv, ppc64, and s390x (c34309bea2, Kevin Buettner)
• Update copyright dates to include 2025 (d01e823438, Tom Tromey)
• gdb: fix building with all targets (65ab41b7d5, Guinevere Larsen)
• gdb: fix riscv record-full push (09338cf326, Timur)
• Many minor typo fixes (973c575967, Tom Tromey)

Notable Changes

• riscv: lib: Add a default implementation of board_fdt_blob_setup (d0969a6b64, Yao Zi)
• Revert "Merge patch series "pxe: Precursor series for supporting read_all() in extlinux / PXE"" (f892a7f397, Tom Rini)
• doc: board: starfive: visionfive2: add missing format command to Flashing (84028132af, E Shattow)
• riscv: dts: jh7110: add DeepComputing FML13V01 device-tree (and 2 more) (7125924a62, Heinrich Schuchardt)
• board: starfive: spl: support DeepComputing FML13V01 (and 3 more) (62dad88db2, Heinrich Schuchardt)
• doc: add DeepComputing FML13V01 documentation (612e832a9c, Heinrich Schuchardt)
• doc: add DeepComputing FML13V01 documentation (9b0a451b9e, Heinrich Schuchardt)
• riscv: dts: k1: add pinctrl property in dts. (d1cea78af4, Huan Zhou)
• board: starfive: visionfive2: Order board detection logic to match config (62ea9c329a, E Shattow)
• board: starfive: visionfive2: Order board detection logic to match config (5ac699efe9, E Shattow)
• riscv: dts: binman.dtsi: Switch to u-boot-nodtb entry for proper U-Boot (efe9c12322, Yao Zi)
• riscv: add initjmp() (3691328ef6, Jerome Forissier)
• riscv: dts: starfive: Prevent binman from relocating symbols in SPL (97b433b4e3, Yao Zi)
• riscv: Provide __image_copy_{start_end} symbols in linkerscript (d3c597f08a, Yao Zi)
• sysreset: diverge GPIO reset and poweroff configs per-phase (782bd104b6, Svyatoslav Ryhel)

Notable Changes

• rustc_target: RISC-V: add base "I"-related important extensions (6f40f0cdab, Tsukasa OI)
• rustc_target: Use "B" shorthand on the RISC-V Android target (52392ec9e1, Tsukasa OI)
• Make target maintainers more easily pingable (864a9ba928, Noratrieb)

Notable Changes

• target: drop unused parameter to target_create() (9a09d38478, Antonio Borneo)
• doc: document changes in rp2xxx flash driver (9fce121366, Tomas Vanek)

Notable Changes

• Optimizing the Implementation of GEMV on the RISC-V V Extension (1ff303f36e, lglglglgy)
• Optimized RVV_ZVL256B Implementation of zgemv_n (7616c42095, guoyuanplct)
• Format the code (11ffc8680e, guoyuanplct)