RISC-V Software News

RISC-V International

The spec repos saw 28 commits this month, led by ISA Manual with 26 commits.

Spec Repository Activity

Repository	Commits	Contributors
ISA Manual	26	16
SBI Spec	1	1
ELF psABI	1	1

Linux Kernel (RISC-V)

71

Commits

33

Contributors

4665

Lines Added

671

Lines Removed

A productive month for Linux Kernel (RISC-V) with 71 commits from 33 contributors. Inochi Amaoto was the most active contributor with 7 commits. New feature work included 29 commits: "RISC-V: KVM: add KVM_CAP_RISCV_MP_STATE_RESET"; "riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10". Platform and DT work accounted for 21 commits. KVM and virtualisation received 9 patches. Work on Smstateen accounted for 9 commits.

29 New features & support 21 Device tree / platform support 9 KVM / Virtualisation 9 ISA extensions 4 Interrupt controllers (AIA/APLIC/PLIC) 4 Bug fixes 4 Cleanup & refactoring 1 Vector extension (RVV)

Notable Changes

riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension (and 3 more) (d9669e33c8, Cyan Yang)
riscv: Add SiFive xsfvfwmaccqqq vendor extension (and 2 more) (34e9b16b4b, Cyan Yang)
crypto: lib/chacha - add array bounds to function prototypes (and 2 more) (bdc2a55687, Eric Biggers)
riscv: dts: spacemit: add gpio LED for system heartbeat (and 3 more) (3aa64cd126, Yixun Lan)
Revert "crypto: run initcalls for generic implementations earlier" (ef93f15628, Herbert Xu)
bpf, riscv64: Support load-acquire and store-release instructions (8afd3170d5, Andrea Parri)
riscv: dts: renesas: Add specific RZ/Five cache compatible (1064013303, Conor Dooley)
bpf, riscv64: Introduce emit_load_*() and emit_store_*() (118ae46b79, Andrea Parri)
riscv: Fix kernel crash due to PR_SET_TAGGED_ADDR_CTRL (ae08d55807, Nam Cao)
riscv: dts: thead: Add device tree VO clock controller (a4c95b924d, Michal Wilczynski)
riscv: dts: spacemit: Add clock tree for SpacemiT K1 (a6fafa64b0, Haylen Chu)
riscv: Disallow PR_GET_TAGGED_ADDR_CTRL without Supm (7f1c3de137, Samuel Holland)
riscv: misaligned: Add handling for ZCB instructions (eb16b3727c, Nylon Chen)
riscv: dts: starfive: fml13v01: enable USB 3.0 port (a2e7f6c487, Sandie Cao)
riscv: sophgo: dts: Add spi controller for SG2042 (73ab31a8f3, Zixian Zeng)

Top Contributors

Author	Commits
Inochi Amaoto	7
Cyan Yang	7
Radim Krčmář	6
E Shattow	4
Yixun Lan	4
Jisheng Zhang	4
Eric Biggers	3
Kevin Brodsky	3
Clément Léger	3
Herbert Xu	3

Mailing List Activity

Re: [PATCH v2 00/57] irqdomain: Cleanups and Documentation — Jiri Slaby
Re: [PATCH 2/2] riscv: uaccess: do not do misaligned accesses in get/put_user() — David Laight
Re: [PATCH] riscv: use generic MMIO accessors — kernel test robot
Re: [PATCH 0/2] riscv: misaligned: fix misaligned accesses handling in put/get_user() — Alexandre Ghiti
Re: [PATCH 2/2] riscv: uaccess: do not do misaligned accesses in get/put_user() — Alexandre Ghiti
Re: [PATCH 1/2] riscv: process: use unsigned int instead of unsigned long for put_user() — Alexandre Ghiti
Re: Broken 32-bit riscv debug build with ZSTD and FTRACE — Marco Bonelli
Re: [PATCH v1 1/1] riscv: fix runtime constant support for nommu kernels — Charles Mirabile
Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042 — Chen Wang
Re: [PATCH v1 1/1] riscv: fix runtime constant support for nommu kernels — Charles Mirabile

OpenSBI

12

Commits

7

Contributors

840

Lines Added

62

Lines Removed

A quieter month for OpenSBI, with 12 commits from 7 contributors. Leading the charge was Anup Patel with 5 commits. Work on Zaamo, Zicntr accounted for 3 commits. The interrupt subsystem got 1 patch of attention this month.

4 Device tree / platform support 3 ISA extensions 2 Bug fixes 1 Interrupt controllers (AIA/APLIC/PLIC)

Notable Changes

lib: sbi: hart: Detect existence of cycle and instret CSRs for Zicntr (7e31dc8052, Yao Zi)
lib: utils/mpxy: Remove p2a_db_index from RPMI system MSI attributes (f3cce5b97f, Anup Patel)
lib: utils/mailbox: Parse A2P doorbell value from DT (and 2 more) (8fadfebdd1, Anup Patel)
lib: utils: fdt: Claim Zicntr if time CSR emulation is possible (60c3f97de8, Yao Zi)
lib: Emulate AMO instructions when Zaamo is not available (8a3071222a, Chao-ying Fu)
lib: utils: Fix fdt_mpxy_init() not returning error code (2bb7632649, Alvin Chang)
Makefile: fix missing .debug_frame DWARF section for GCC (017a161788, Parshintsev Anatoly)
lib: sbi: pmu: Return SBI_EINVAL if cidx_mask is 0 (69a0f0245f, James Raphael Tiovalen)
include: sbi: Change SBI spec version to 3.0 (d4f5a16598, Anup Patel)
lib: sbi: Use hsm stop for hsm wait (d844deadec, Nick Hu)

Top Contributors

Author	Commits
Anup Patel	5
Yao Zi	2
James Raphael Tiovalen	1
Alvin Chang	1
Chao-ying Fu	1
Parshintsev Anatoly	1
Nick Hu	1

Notable Discussions

[PATCH] lib: sbi: pmu: Rework SSE callbacks 1 replies — Atish Patra
Register Zicntr in FDT when emulating is possible 5 replies — Yao Zi
[PATCH] lib: sbi: Only enable TM bit in scounteren 3 replies — Jessica Clarke
[PATCH] lib: sbi: Revert entry_count before doing hsm stop in hsm wait loop 3 replies — Nick Hu
platform: generic: mips: add an entry function (3-patch series) 3 replies — Anup Patel

Mailing List Activity

lib: sbi: pmu: Add SSE register/unregister() callbacks 2 — Clément Léger
[PATCH] lib: utils: hsm: Do not fail on EALREADY in rpmi-hsm fixup. 1 — 王子昂
[PATCH] lib: sbi: dbtr: Fix shared memory layout 1 — Charlie Jenkins
Support external CMO to flush entire cache 1 — Anup Patel
*** Add MIPS P8700 platform *** 1 — Chao-ying Fu
[PATCH] lib: utils: Initial compiler built-in stack protector support — Yu-Chien Lin
[PATCH] lib: sbi: pmu: Return SBI_EINVAL if cidx_mask is 0 in ctr_cfg_match — James R T

QEMU (RISC-V)

81

Commits

12

Contributors

2417

Lines Added

1600

Lines Removed

A productive month for QEMU (RISC-V) with 81 commits from 12 contributors. Top contributor: Paolo Bonzini with 27 commits. Vector extension support moved forward with 12 commits. KVM and virtualisation received 10 patches. New feature work included 10 commits: "kvm: Introduce kvm_arch_pre_create_vcpu()"; "target/riscv: add more RISCVCPUDef fields". Bug fixes accounted for 7 commits (8%).

12 Vector extension (RVV) 10 KVM / Virtualisation 10 New features & support 7 Bug fixes 4 Device tree / platform support 3 ISA extensions 1 Security & memory safety fixes

Notable Changes

target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions (and 6 more) (db21c3eb05, Max Chou)
hw/riscv/virt-acpi-build: Add support for RIMT (cd18dbbf9d, Sunil V L)
target/riscv: rvv: Source vector registers cannot overlap mask register (3e8d1e4a62, Anton Blanchard)
hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure (d2a88aca76, Sunil V L)
hw/riscv: acpi: only create RHCT MMU entry for supported types (82c81c07e8, Paolo Bonzini)
target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS (b0450a101d, Anton Blanchard)
Generate strided vector loads/stores with tcg nodes. (28c12c1f2f, Paolo Savini)
target/riscv/kvm: add scounteren CSR (and 8 more) (8ab99a05f3, Daniel Henrique Barboza)
kvm: Introduce kvm_arch_pre_create_vcpu() (a668268dc0, Xiaoyao Li)
target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores. (9425790ace, Paolo Savini)
target/riscv: pmp: remove redundant check in pmp_is_locked (and 4 more) (986222f0f9, Loïc Lefort)
target/riscv: Fix the rvv reserved encoding of unmasked instructions (8539a1244b, Max Chou)
hw/riscv/virt.c: remove 'long' casts in fmt strings (and 8 more) (e7cb99bfd1, Daniel Henrique Barboza)
target/riscv: fix endless translation loop on big endian systems (ad63158bdb, Ziqiao Kong)
target/riscv: th: make CSR insertion test a bit more intuitive (1d84c2401c, Paolo Bonzini)

Top Contributors

Author	Commits
Paolo Bonzini	27
Daniel Henrique Barboza	18
Richard Henderson	8
Max Chou	8
Loïc Lefort	5
Sebastian Huber	4
Anton Blanchard	3
Paolo Savini	3
Sunil V L	2
Xiaoyao Li	1

Notable Discussions

[PATCH] target/riscv: remove capital 'Z' CPU properties — Daniel Henrique Barboza
Re: [PATCH v4 00/27] hw/i386/pc: Remove deprecated 2.6 and 2.7 PC machines — Peter Krempa
Re: [PATCH v4 00/27] hw/i386/pc: Remove deprecated 2.6 and 2.7 PC machines — Michael S. Tsirkin

Mailing List Activity

Re: [qemu PATCH 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa — Andrew Jones
Re: [PATCH REPOST v4 0/4] acpi: Add machine option to disable SPCR table — Michael S. Tsirkin
Re: [PATCH v4 0/2] Extend and configure PMP region count — Alistair Francis
[qemu PATCH 2/3] target/riscv/cpu.c: add 'ssstrict' to riscv,isa — Daniel Henrique Barboza
[qemu PATCH 0/3] target/riscv: add missing named features — Daniel Henrique Barboza
[qemu PATCH 1/3] target/riscv/cpu.c: add 'sdtrig' in riscv,isa — Daniel Henrique Barboza
[qemu PATCH 3/3] target/riscv/cpu.c: do better with 'named features' doc — Daniel Henrique Barboza
[PATCH v5] target/riscv/kvm: add satp mode for host cpu — Meng Zhuo
[PATCH v3] migration: Fix migration failure when aia is configured as aplic-imsic — liu.xuemei1
[PATCH] hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register — Nutty Liu

GCC (RISC-V)

61

Commits

15

Contributors

4743

Lines Added

779

Lines Removed

GCC (RISC-V) had a solid month with 61 commits from 15 contributors. Leading the charge was Jeff Law with 13 commits. New feature work included 15 commits: "RISC-V: Add minimal support of double trap extension 1.0"; "[RISC-V] Add andi+bclr synthesis". ISA extension work spanned 12 commits, touching Smnpm, Ssnpm, Svadu. RVV work continued with 9 commits touching vector-related code. Compiler backend and code generation improvements accounted for 9 commits. The thread "RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn" generated notable discussion with 12 replies.

15 New features & support 12 ISA extensions 9 Vector extension (RVV) 9 Compiler backend / code generation 5 Bug fixes 3 Cleanup & refactoring 2 Performance optimisations 1 KVM / Virtualisation

Notable Changes

[PATCH v2 2/2] MIPS p8700 doesn't have vector extension and added the dummies reservation for the same. (18f272ec33, Umesh Kalappa)
[PATCH v2 1/2] The following changes enable P8700 processor for RISCV and P8700 is a high-performance processor from MIPS by extending RISCV with custom instructions (1186a2bd6e, Umesh Kalappa)
RISC-V: Add minimal support of double trap extension 1.0 (077cdc9dc0, Jerry Zhang Jian)
RISC-V: Minimal support for ssnpm, smnpm and smmpm extensions. (and 2 more) (7e5f5fd101, Dongyan Chen)
RISC-V: Add augmented hypervisor series extensions. (0cbace3b14, Jiawei)
RISC-V: Add new operand constraint: cR (c9eb473fb9, Kito Cheng)
RISC-V: Leverage vaadd.vv for signed standard name avg_ceil (and 10 more) (6bcd522438, Pan Li)
[PATCH] RISC-V: Recognized svadu and svade extension (aed2a447c7, Mingzhu Yan)
RISC-V: Since the loop increment i++ is unreachable, the loop body will never execute more than once (55cfd1c8fa, Jin Ma)
RISC-V: Support Zilsd code gen (and 8 more) (a3e78dda4d, Kito Cheng)
[RISC-V][PR target/120137][PR target/120154] Don't create out-of-range permutation constants (49c44911df, Jeff Law)
RISC-V: Support RISC-V Profiles 20/22. (43b450e3f7, Jiawei)
[RISC-V] Add andi+bclr synthesis (c86125a62d, Shreya Munnangi)
[to-be-committed][RISC-V] Adjust testcases and finish register move costing fix (005424e333, Jeff Law)
RISC-V: Avoid division by zero in check_builtin_call [PR120436]. (and 3 more) (6ccf845d9f, Robin Dapp)

Top Contributors

Author	Commits
Jeff Law	13
Pan Li	12
Kito Cheng	10
Shreya Munnangi	7
Robin Dapp	4
Dongyan Chen	3
Umesh Kalappa	2
Jin Ma	2
Jiawei	2
Jerry Zhang Jian	1

Notable Discussions

RISC-V: frm/mode-switch: remove dubious frm edge insertion before call_insn 12 replies — Jeff Law

LLVM (RISC-V)

196

Commits

38

Contributors

35047

Lines Added

10664

Lines Removed

It was a busy month in LLVM (RISC-V) land, with 196 commits from 38 contributors. That's +35,047/-10,664 lines of churn. Top contributor: Craig Topper with 42 commits. New feature work included 74 commits: "[RISCV] Add shlcofideleg extension (#141572)"; "[RISCV] Add ORC_B to SimplifyDemandedBitsForTargetNode. (#141975)". ISA extension work spanned 47 commits, touching QC_E_ADDI, QC_E_J, QC_E_LI, Zdinx, Zicbop, Zicsr. Backend and code generation work was the biggest theme at 40 commits.

74 New features & support 47 ISA extensions 47 Cleanup & refactoring 40 Compiler backend / code generation 14 Bug fixes 13 Vector extension (RVV) 4 Performance optimisations 1 Interrupt controllers (AIA/APLIC/PLIC)

Notable Changes

[RISCV] Add Andes XAndesVPackFPH (Andes Vector Packed FP16) extension. (#138827) (9e27db0a50, Jim Lin)
[RISCV] Add Andes XAndesVDot (Andes Vector Dot Product) extension. (#139849) (2a8960e48b, Jim Lin)
[IA][RISCV] Add support for vp.load/vp.store with shufflevector (#135445) (63fcce6611, Min-Yih Hsu)
[RISCV][TII] Add and use new hook to simplify/canonicalize instructions after MachineCopyPropagation (#137973) (52b345d036, Alex Bradbury)
[RISCV][MC] Add support for Q extension (#139369) (1e503d08e1, Iris Shi)
[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131005) (0ab67ec191, Min-Yih Hsu)
[RISCV] Migrate getConstant indexed insert/extract subvector to new API (#139111) (54bb2295c3, Philip Reames)
[RISCV] Use RISCVRegisterInfo::isRVVRegClass to replace IsScalableVector in storeRegToStackSlot/loadRegFromStackSlot. NFC (#139979) (426573332c, Craig Topper)
[RISCV][Scheduler] Split `UnsupportedSchedZfa` by other fp extensions (#140186) (1c2c02c8cb, Iris Shi)
[DAG] Add wrappers for insert_vector_elt and extract_vector_elt [nfc] (#139141) (80370465d9, Philip Reames)
[RISCV] Add tests for widening fixed vector masked loads/stores. NFC (#140949) (6212c199b1, Craig Topper)
[RISCV] Support scalable vectors for the zvqdotq lowering paths (#140922) (68995b18da, Philip Reames)
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495) (99e8d22d69, Iris Shi)
[RISCV][test] Add (add x, C) -> (sub x, -C) multi-use and vector tests (e618a79711, Piotr Fusik)
[DAG] Add wrappers for insert and extract sub-vector [nfc] (#137230) (6e654caabe, Philip Reames)

Top Contributors

Author	Commits
Craig Topper	42
Philip Reames	28
Fangrui Song	24
Jim Lin	13
Iris Shi	11
Sudharsan Veeravalli	10
Kazu Hirata	9
Min-Yih Hsu	8
Alex Bradbury	5
Luke Lau	4

glibc (RISC-V)

3

Commits

1

Contributors

34

Lines Added

0

Lines Removed

glibc (RISC-V) was quiet this month with 3 commits. Joseph Myers dominated with 3/3 commits (100%).

2 New features & support

Notable Changes

Implement C23 compoundn (ae31254432, Joseph Myers)
Implement C23 rootn. (06caf53adf, Joseph Myers)
Update syscall lists for Linux 6.15 (eaf88c1025, Joseph Myers)

Top Contributors

Author	Commits
Joseph Myers	3

Notable Discussions

[PATCH] riscv: Correct __riscv_hwprobe function attributes [BZ #32932] 5 replies — enh
[PATCH v2] riscv: Correct __riscv_hwprobe function prototype [BZ #32932] 5 replies — enh

Binutils (RISC-V)

15

Commits

6

Contributors

497

Lines Added

51

Lines Removed

A steady month for Binutils (RISC-V) with 15 commits from 6 contributors. Jiawei was the most active contributor with 5 commits. New feature work included 9 commits: "RISC-V: Add support for RISC-V Profiles 23."; "RISC-V: Add support for RISC-V Profiles 20/22.". RVV work continued with 2 commits touching vector-related code. Virtualisation work accounted for 1 patch, continuing to mature RISC-V KVM support.

9 ISA extensions 9 New features & support 2 Vector extension (RVV) 1 KVM / Virtualisation

Notable Changes

RISC-V: Added vendor extensions, xmipscbop, xmipscmov, xmipsexectl and xmipslsp (617ead3c20, Chao-ying Fu)
RISC-V: Add implication from the XTheadZvamo extension (and 4 more) (be28a26aeb, Tsukasa OI)
RISC-V: Add support for RISC-V Profiles 23. (and 4 more) (a3d6596ecf, Jiawei)
RISC-V: Add zilsd & zclsd support (bbac5532cc, dysun)
RISC-V: Support Zce 1.0 (b304edbeb6, Jerry Zhang Jian)
Reduce rs_align_code memory for small alignments (5e5f37ed00, Alan Modra)
elf symbol size (bcbba25dfc, Alan Modra)

Top Contributors

Author	Commits
Jiawei	5
Tsukasa OI	5
Alan Modra	2
dysun	1
Jerry Zhang Jian	1
Chao-ying Fu	1

U-Boot (RISC-V)

18

Commits

3

Contributors

511

Lines Added

100

Lines Removed

U-Boot (RISC-V) kept moving with 18 commits from 3 contributors. Most of the work came from Yao Zi (12 of 18 commits, 66%). Board and device tree support got 8 commits.

8 Device tree / platform support 5 New features & support 1 Bug fixes

Notable Changes

board: thead: licheepi4a: Enable SPL support (38ed760bc9, Yao Zi)
riscv: lib: Split out support for T-Head cache management operations (3dbff9eecc, Yao Zi)
riscv: dts: jh7110: override syscrg assigned clock rates with defaults (bbf5f79bba, E Shattow)
riscv: Access gd with inline assembly when building with LTO or Clang (307666be28, Yao Zi)
riscv: starfive: jh7110: move uart0 clock frequency to config header (97833f4cf6, E Shattow)
riscv: dts: th1520: Complete clock tree (and 5 more) (ff6e20c32f, Yao Zi)
riscv: cpu: th1520: Select clock driver (and 2 more) (1d759cc0ad, Yao Zi)
riscv: dts: jh7110: remove redundant parent nodes (8b43f4a7be, E Shattow)
booti/bootm: riscv: Verify image arch type (37b0b22d8b, Mayuresh Chitale)
riscv: Select appropriate image type (027a316828, Mayuresh Chitale)
riscv: insn-def.h: Fix header guard (fa317411ba, Mayuresh Chitale)

Top Contributors

Author	Commits
Yao Zi	12
E Shattow	3
Mayuresh Chitale	3

Rust (RISC-V)

1

Commits

1

Contributors

0

Lines Added

1

Lines Removed

One lone commit for Rust (RISC-V) this month.

1 ISA extensions

Notable Changes

zkvm: remove schmerik from maintainers list (77876b5233, Erik Kaneda)

Top Contributors

Author	Commits
Erik Kaneda	1

OpenOCD (RISC-V)

5

Commits

2

Contributors

79

Lines Added

59

Lines Removed

Not the busiest month for OpenOCD (RISC-V): 5 commits from 2 contributors. Antonio Borneo was the driving force, authoring 4 of 5 commits (80%).

1 Bug fixes

Notable Changes

adapter: list supported transports beside adapter name (da50873d5e, Antonio Borneo)
transport: allow transport name jtag/swd for hla and dapdirect (c1c4d489df, Antonio Borneo)
stlink: simplify the use of deprecated HLA transport (420f637cab, Antonio Borneo)
target: armv7a: drop command 'cache_config l2x' (d71ed4f3bc, Antonio Borneo)
doc/openocd: Fix Tcl spelling (98c95df228, Marc Schink)

Top Contributors

Author	Commits
Antonio Borneo	4
Marc Schink	1

OpenBLAS (RISC-V)

6

Commits

2

Contributors

1957

Lines Added

31

Lines Removed

Not the busiest month for OpenBLAS (RISC-V): 6 commits from 2 contributors. guoyuanplct dominated with 5/6 commits (83%). 1 commit targeted performance improvements.

2 New features & support 1 ISA extensions 1 Bug fixes 1 Performance optimisations

Notable Changes

kernel/riscv64:Added support for omatcopy on riscv64. (4d213653d8, guoyuanplct)
kernel/riscv64:Fixed the bug of openblas_utest_ext failing in c/zgemv and some c/zgbmv tests: (9a7e3f102b, guoyuanplct)
Optimized the axpby function. (45fd2d9b07, guoyuanplct)
add shgemm for RISCV_ZVL128B (2996c25c94, Srangrang)
Format Code (be9f7550b5, guoyuanplct)
del lines (d2003dc886, guoyuanplct)

Top Contributors

Author	Commits
guoyuanplct	5
Srangrang	1

Linux Kernel Docs & DT (RISC-V)

4

Commits

2

Contributors

29

Lines Added

0

Lines Removed

Minimal activity in Linux Kernel Docs & DT (RISC-V): 4 commits from 2 contributors. Cyan Yang dominated with 3/4 commits (75%).

4 New features & support 4 Device tree / platform support 3 ISA extensions

Notable Changes

dt-bindings: riscv: Add xsfvfwmaccqqq ISA extension description (and 2 more) (d5ca02b25f, Cyan Yang)
dt-bindings: riscv: sophgo: Add SG2044 compatible string (22db96e4ab, Inochi Amaoto)

Top Contributors

Author	Commits
Cyan Yang	3
Inochi Amaoto	1

The Big Picture

RISC-V International

Spec Repository Activity

Linux Kernel (RISC-V)

Notable Changes

Top Contributors

Mailing List Activity

OpenSBI

Notable Changes

Top Contributors

Notable Discussions

Mailing List Activity

QEMU (RISC-V)

Notable Changes

Top Contributors

Notable Discussions

Mailing List Activity

GCC (RISC-V)

Notable Changes

Top Contributors

Notable Discussions

LLVM (RISC-V)

Notable Changes

Top Contributors

glibc (RISC-V)

Notable Changes

Top Contributors

Notable Discussions

Binutils (RISC-V)

Notable Changes

Top Contributors

U-Boot (RISC-V)

Notable Changes

Top Contributors

Rust (RISC-V)

Notable Changes

Top Contributors

OpenOCD (RISC-V)

Notable Changes

Top Contributors

OpenBLAS (RISC-V)

Notable Changes

Top Contributors

Linux Kernel Docs & DT (RISC-V)

Notable Changes

Top Contributors