RISC-V Software News

Spec Repository Activity

Notable Changes

• Add a new optional ",cma" suffix to the crashkernel= command line option (35c18f2933, Jiri Bohac)
• riscv: optimize gcd() performance on RISC-V without Zbb extension (36e2241687, Kuan-Wei Chiu)
• RISC-V: KVM: add SBI extension init()/deinit() functions (cf648c400f, Clément Léger)
• riscv: defconfig: Enable PWM support for SpacemiT K1 SoC (9df56b46cd, Guodong Xu)
• riscv: dts: spacemit: add reset support for the K1 SoC (2c0cf4fed0, Alex Elder)
• riscv: dts: spacemit: add PWM support for K1 SoC (66f56c7a64, Guodong Xu)
• RISC-V: KVM: add SBI extension reset callback (c046de827c, Clément Léger)
• riscv: add Andes SoC family Kconfig support (00dba19aa0, Ben Zong-You Xie)
• riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree (and 5 more) (6ea2a06165, Han Gao)
• riscv/bug: Add ARCH_WARN_ASM macro for BUG/WARN asm code sharing with Rust (8ad470d4e3, FUJITA Tomonori)
• riscv: optimize gcd() code size when CONFIG_RISCV_ISA_ZBB is disabled (26b537edc5, Kuan-Wei Chiu)
• riscv: dts: starfive: jh7110-common: add status power led node (1ec99dfe9e, E Shattow)
• riscv: defconfig: spacemit: enable sdhci driver for K1 SoC (bd4d5d3faa, Yixun Lan)
• irqchip/riscv-imsic: Add kernel parameter to disable IPIs (ea92b6046d, Anup Patel)
• riscv: dts: sophgo: add SG2044 SPI NOR controller driver (162b265ce0, Longbin Li)

Notable Changes

• include: sbi: fix swap errors with newer gcc -Werror=sequence-point (663b05a5f7, Ben Dooks)
• firmware: payload: test: Add SBI shutdown call after test message (3876f8cd1e, Xiang W)
• lib: sbi: Remove redundant call to sbi_hart_expected_trap_addr() (ea5abd1f5e, Alvin Chang)
• firmware: Initial compiler built-in stack protector support (edfbc1285d, Alvin Chang)
• lib: sbi_list: add a helper for safe list iteration (61083eb504, Yong-Xuan Wang)
• lib: sbi: Only enable TM bit in scounteren (5b305e30a5, Atish Patra)
• firmware: Replace sole uses of REGBYTES with __SIZEOF_LONG__ (079bf6f0f9, Jessica Clarke)
• firmware: Rename __rel_dyn_start/end to __rela_dyn_start/end (e10a45752f, Jessica Clarke)
• lib: utils/serial: Clear LSR status and check RBR status (b8f370aa37, Yi Pei)
• include: sbi: Remove unused (LOG_)REGBYTES (and 2 more) (cc546e1a06, Jessica Clarke)
• platform: openpiton: fix uninitialized plic_data struct (0b7c2e0d60, Manuel Hernández Méndez)
• lib: utils: fdt: fix "ranges" translation (84044ee83c, Max Hsu)

Notable Changes

• target: riscv: Add Svrsw60t59b extension support (dc8bffc4eb, Alexandre Ghiti)
• target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction (5625817e8b, Vasilis Liaskovitis)
• hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype (29abd3d112, Huang Borong)
• riscv: Revert "Generate strided vector loads/stores with tcg nodes." (09ac27a9b5, Daniel Henrique Barboza)
• target/riscv: support atomic instruction fetch (Ziccif) (and 3 more) (f9eaa1542b, Jim Shu)
• target/riscv/tcg: decouple profile enablement from user prop (f655704c3d, Daniel Henrique Barboza)
• target/riscv/kvm: add max_satp_mode from host cpu (b0175841fa, Meng Zhuo)
• target/riscv: Add BOSC's Xiangshan Kunminghu CPU (60aab7ad11, Huang Borong)
• acpi: Add machine option to disable SPCR table (54401d5abd, Li Chen)
• target/riscv: do not call GETPC() in check_ret_from_m_mode() (and 3 more) (16aa7771af, Daniel Henrique Barboza)
• target/riscv/cpu.c: do better with 'named features' doc (and 3 more) (5ee4f21713, Daniel Henrique Barboza)
• target/riscv: Restrict midelegh access to S-mode harts (and 3 more) (86bc3a0abf, Jay Chang)
• hw/riscv/riscv-iommu: Fix PPN field of Translation-reponse register (5000ba0cb1, Nutty Liu)
• target/riscv: Fix exception type when VU accesses supervisor CSRs (30ef718423, Xu Lu)
• target/riscv/tcg: restrict satp_mode changes in cpu_set_profile (a429f9304d, Daniel Henrique Barboza)

Notable Changes

• RISC-V: Add support for resumable non-maskable interrupt (RNMI) handlers (1603eeb6c8, Christoph Müllner)
• [PATCH] RISC-V: Vector-scalar widening negate-multiply-(subtract-)accumulate [PR119100] (a0e28fd03f, Paul-Antoine Arras)
• [PATCH v2] RISC-V: Vector-scalar widening multiply-(subtract-)accumulate [PR119100] (99a3c71db6, Paul-Antoine Arras)
• RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost (and 9 more) (b953374ec9, Pan Li)
• [RISC-V][PR target/120642] Avoid propagating constant AVL for theadvector (f2e3886a30, Jeff Law)
• RISC-V: riscv-ext.def: Add allocated group IDs and group bit positions (7ac42d3d7c, Christoph Müllner)
• [RISC-V] Add missing insn types to xiangshan.md and mips-p8700.md (00e1be7b34, Jeff Law)
• vect: Add is_gather_scatter argument to misalignment hook. (de75875d67, Robin Dapp)
• [PATCH v5] RISC-V: Mips P8700 Conditional Move Support. (3fbed69502, Umesh Kalappa)
• [RISC-V] Add basic instrumentation to fusion detection (053a678cc5, Shreya Munnangi)
• RISC-V: Adding H to the canonical order [PR121312] (da88f9bd9e, Kito Cheng)
• [RISC-V] Restrict generic-vector-ooo DFA (55abb0d57c, Jeff Law)
• [RISC-V] Detect new fusions for RISC-V (742f556226, Daniel Barboza)
• [RISC-V][PR target/118886] Refine when two insns are signaled as fusion candidates (83d19b5d84, Jeff Law)
• [PATCH] [RISC-V] Fix shift type for RVV interleaved stepped patterns [PR120356] (9c1ed63e4c, Alexey Merzlyakov)

Notable Changes

• [RISCV][VLOPT] Add support for vector integer add-with-carry/subtract-with-borrow instructions (#148247) (a606f4441a, Mikhail R. Gadelha)
• [RISCV] Avoid vl toggles when lowering vector_splice/experimental_vp_splice and add +vl-dependent-latency tuning feature (#146746) (7c812ea01a, Luke Lau)
• [RISCV] Add Andes XAndesVSIntLoad (Andes Vector INT4 Load) extension (#147005) (3f33e7ba5b, Jim Lin)
• [RISCV] Add UnsupportedSchedXXX for vendor extensions package (#147666) (b57df56b48, Pengcheng Wang)
• [RISCV] Remove incorrect and untested FrameIndex support from SelectAddrRegImm9. (#148779) (63d099af14, Craig Topper)
• Revert "[RISCV][TTI] Enable masked interleave access for scalable vector (#149981)" (5294793bdc, Alex Bradbury)
• [IA] Add masked.load/store support for shuffle (de)interleave load/store (#150241) (992118cb4d, Philip Reames)
• [RISCV] Add copies to physical registers in VL optimizer tests. NFC (#151170) (9b23e2bf8d, Luke Lau)
• [RISCV] Correct stride for strided load/store of vectors of pointers in lowerInterleavedLoad/lowerInterleavedStore. (#147598) (be19a27cc5, Craig Topper)
• [RISCV][TTI] Enable masked interleave access for scalable vector (#149981) (ee3a7714b7, Mel Chen)
• [RISCV][TTI] Implement vector costs for `llvm.fpto{u|s}i.sat()`. (#143655) (324773e238, Elvis Wang)
• [RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563) (22707fd4a5, Jim Lin)
• [RISCV] Added the MIPS prefetch extensions for MIPS RV64 P8700. (#145647) (032966ff56, UmeshKalappa)
• [RISCV] Add ISel patterns for Qualcomm uC Xqcicli extension (#148121) (0be51cff91, quic_hchandel)
• [RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (#146675) (66969c9494, quic_hchandel)

Notable Changes

• RISC-V: Don't allocate dynamic relocation if it's section was discarded (and 8 more) (f6fc2b5231, Nelson Chu)
• RISC-V: Fix libpath_suffix selection for ldscript (6589a725f0, Mark Goncharov)
• RISC-V: Bind defined symbol locally in PIE (39c7793ba8, Linsen Zhou)
• gas various other const pointer changes (d24a60f9fc, Alan Modra)
• METAG_RELOC_AGAINST_DISCARDED_SECTION (71931bcce1, Alan Modra)
• gas remove assorted unnecessary casts (e76715632c, Alan Modra)
• gas various other void* casts (a5b6fadf88, Alan Modra)
• gas alloc casts (60ba816bc1, Alan Modra)
• gas NULL casts (1a12e548ba, Alan Modra)

Notable Changes

• sim: riscv: Fix build issue due to INSN_CLASS_C was changed to INSN_CLASS_ZCA (a6a177d0a2, Nelson Chu)
• gdb/risc-v: fix ISA string detection for disassembly (1324b95f57, Marek Pikuła)
• gdb: remove unused includes (05ef43a2e7, Simon Marchi)

Notable Changes

• riscv: add build support for big-endian (7bd65e89ad, Ben Dooks)
• riscv: dts: th1520: Describe GMACs and enable them on Lichee Pi 4A (and 2 more) (e875813600, Yao Zi)
• riscv: aclint_ipi: Support T-Head C900 CLINT (4153ceb0fe, Yao Zi)
• riscv: byteorder: add test for big-endian (364627596c, Ben Dooks)
• riscv: cpu: th1520: Limit upper RAM boundary to 4 GiB (and 3 more) (12b90ea3c2, Yao Zi)
• treewide: Remove empty board_init() function from all boards (70a4d1fa1d, Sam Protsenko)
• board: thead: licheepi4a: Bring up secondary cores in SPL (a23c1b3fc0, Yao Zi)

Notable Changes

• Make tier 3 musl targets link dynamically by default (effcd54060, Jens Reidel)
• Rename `tests/assembly` into `tests/assembly-llvm` (ed93c1783b, Guillaume Gomez)

Notable Changes

• jtag: drivers: xlnx-axi-xvc: Add support for Xilinx XVC over direct bus interface (AXI) (a192949095, Nicolas Derumigny)

Notable Changes

• Fix bad vector zero initializer and other compiler warnings for RISC-V. (72f082f31d, Chip Kerchner)
• Declare the "small" kernel static in addition to inline (e2d941e9af, Martin Kroeker)
• Declare the "small" kernel static in addition to inline (8214700930, Martin Kroeker)

Notable Changes

• dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 (610f943a66, Alexander Sverdlin)
• dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings (12d8c15992, Ben Zong-You Xie)
• dt-bindings: riscv: cpus: Add AMD MicroBlaze V 64bit compatible (28fa0dcb57, Michal Simek)