In August 2025, the RISC-V ecosystem saw 277 commits across 12 projects. LLVM (RISC-V) led with 172 commits (62%). Also active: GCC (RISC-V) (30), Linux Kernel (RISC-V) (25), QEMU (RISC-V) (9). Software support advanced for QC_INSB, QC_INSBI, Smctr, Ssctr, Zacas, Zicond, Zvbb, Zvbc. Most-discussed mailing list thread: "RISC-V: Don't generate R_RISCV_RELATIVE if symbol referenced section is SH_ABS" (Binutils (RISC-V), 8 replies).
RISC-V International
The spec repos saw 33 commits this month, led by ISA Manual with 32 commits.
Spec Repository Activity
Repository
Commits
Contributors
ISA Manual
32
12
ELF psABI
1
1
Linux Kernel (RISC-V)
25
Commits
14
Contributors
357
Lines Added
469
Lines Removed
Linux Kernel (RISC-V) saw moderate activity with 25 commits from 14 contributors. The codebase got leaner: +357/-469. Pu Lehui was the most active contributor with 9 commits. New feature work included 11 commits: "riscv: dts: thead: th1520: Add IMG BXM-4-64 GPU node"; "riscv: dts: spacemit: add UART resets for Soc K1". Platform and DT work accounted for 6 commits. Virtualisation work accounted for 3 patches, continuing to mature RISC-V KVM support. Interrupt controller infrastructure (AIA/APLIC/PLIC/IMSIC) received 3 patches.
11 New features & support6 Device tree / platform support3 KVM / Virtualisation3 Interrupt controllers (AIA/APLIC/PLIC)3 Bug fixes2 ISA extensions1 Cleanup & refactoring1 Performance optimisations
Notable Changes
riscv, bpf: Add support arena atomics for RV64 (and 7 more) (fb7cefabae, Pu Lehui)
riscv: Separate toolchain support dependency from RISCV_ISA_ZACAS (ec74ae5662, Pu Lehui)
riscv: dts: spacemit: Add OrangePi RV2 board device tree (bab8dea259, Hendrik Hamerlinck)
A steady month for GCC (RISC-V) with 30 commits from 13 contributors. Top contributor: Jeff Law with 7 commits. Compiler backend and code generation improvements accounted for 12 commits. RVV work continued with 7 commits touching vector-related code. New feature work included 7 commits: "RISC-V: Add patterns for vector-scalar IEEE floating-point min"; "RISC-V: Add pattern for vector-scalar floating-point min". Bug fixes accounted for 4 commits (13%).
12 Compiler backend / code generation7 Vector extension (RVV)7 New features & support4 Bug fixes3 Cleanup & refactoring2 ISA extensions
Notable Changes
RISC-V: MIPS prefetch extensions for MIPS RV64 P8700 and can be enabled with xmipscbop. (ef5f0e9c51, Umesh Kalappa)
RISC-V: Add patterns for vector-scalar IEEE floating-point min (and 3 more) (79e0dbf1c4, Paul-Antoine Arras)
RISC-V: Expand const_vector with 2 elts per pattern. (980e1fc195, Robin Dapp)
Improve initial code generation for addsi/adddi (1b5b461428, Shreya Munnangi)
RISC-V: Replace deprecated FUNCTION_VALUE/LIBCALL_VALUE macros with target hooks (and 2 more) (d914cb6743, Kito Cheng)
[RISC-V][PR target/121531] Cover missing insn types in p400 and p600 scheduler models (07b74430df, Jeff Law)
RISC-V: Combine vec_duplicate + vnmsac.vv to vnmsac.vx on GR2VR cost (and 6 more) (44054e6206, Pan Li)
[PR target/119275][RISC-V] Avoid calling gen_lowpart in cases where it would ICE (44cd33881f, Jeff Law)
RTEMS: Add riscv multilibs (73a2a9d6c2, Sebastian Huber)
[RISC-V][PR target/121548] Avoid bogus index into recog operand cache (25bbc0f20a, Jeff Law)
[RISC-V][PR target/121113] Handle HFmode in various insn reservations (2e2589616a, Jeff Law)
LLVM (RISC-V) saw heavy activity with 172 commits from 44 contributors. A hefty +61,955/-6,391 line diff. Leading the charge was Craig Topper with 49 commits. New feature work included 55 commits: "[RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191)"; "[RISCV] Add test coverage for reassociation with poison generating flags". The compiler backend saw heavy activity with 33 commits touching code generation. Work on QC_INSB, QC_INSBI, Smctr, Ssctr, Zicond, Zvbb accounted for 22 commits.
55 New features & support53 Cleanup & refactoring33 Compiler backend / code generation22 ISA extensions9 Vector extension (RVV)8 Performance optimisations5 Bug fixes1 Interrupt controllers (AIA/APLIC/PLIC)
Notable Changes
[CodeGen][RISCV] Add support of RISCV nontemporal to vector predication instructions. (#153033) (658a931c5b, daniel-trujillo-bsc)
GDB (RISC-V) was quiet this month with 2 commits from 2 contributors. Code housekeeping was a significant theme at 1 commit (50%).
1 New features & support1 Cleanup & refactoring
Notable Changes
gdb/record: Support wfi, sfence.vma, sret and mret instructions in risc-v (a784750d16, timurgol007)
gdb: rename gdbarch_software_single_step -> gdbarch_get_next_pcs (1d5f884e50, Simon Marchi)
Top Contributors
Author
Commits
timurgol007
1
Simon Marchi
1
U-Boot (RISC-V)
8
Commits
4
Contributors
336
Lines Added
23
Lines Removed
Not the busiest month for U-Boot (RISC-V): 8 commits from 4 contributors. Michal Simek was the most active contributor with 4 commits. Interrupt controller infrastructure (AIA/APLIC/PLIC/IMSIC) received 1 patch.
3 New features & support2 Bug fixes2 Device tree / platform support1 Interrupt controllers (AIA/APLIC/PLIC)
Notable Changes
riscv: board: Add Andes Voyager board Kconfig support (87f98d9225, Leo Yu-Chi Liang)
riscv: cpu: Use CONFIG_IS_ENABLED(CPU) instead of plain ifdef (c64fc632a8, Michal Simek)
riscv: dts: andes: Add Voyager device tree (a25e1aacdb, Leo Yu-Chi Liang)
xilinx: mbv: Use separate DTB for binman nodes (and 2 more) (87bd5806e6, Michal Simek)
arch/riscv/lib: update memmove and memcpy for big-endian (35d6caad6d, Ben Dooks)
starfive: fix return code of `mac write_eeprom` (909ceacf4a, Heinrich Schuchardt)
Top Contributors
Author
Commits
Michal Simek
4
Leo Yu-Chi Liang
2
Ben Dooks
1
Heinrich Schuchardt
1
Rust (RISC-V)
6
Commits
4
Contributors
128
Lines Added
36
Lines Removed
Rust (RISC-V) saw lighter activity with 6 commits from 4 contributors.
4 New features & support
Notable Changes
Add new Tier-3 target: riscv64a23-unknown-linux-gnu (a4cf5e9eca, Chen Zhongyao)