September 2025 saw 403 commits land across 12 tracked projects. The most active projects were LLVM (RISC-V) (172), Linux Kernel (RISC-V) (121), GCC (RISC-V) (49). Software support advanced for QC_E_LI, Zaamo, Zalrsc, Zfh, Zfhmin, Zibi, Zicbom, Zicbop. Virtualisation saw 19 KVM-related patches. Most-discussed mailing list thread: "RISC-V: Allow VLS types using up to LMUL 8" (GCC (RISC-V), 21 replies).
RISC-V International
The spec repos saw 27 commits this month, led by ISA Manual with 21 commits.
Spec Repository Activity
Repository
Commits
Contributors
ISA Manual
21
9
Profiles
4
1
ELF psABI
2
1
Linux Kernel (RISC-V)
121
Commits
50
Contributors
4240
Lines Added
1079
Lines Removed
It was a busy month in Linux Kernel (RISC-V) land, with 121 commits from 50 contributors. Top contributor: Nam Cao with 12 commits. New feature work included 50 commits: "RISC-V: Enable GPIO keyboard and event device in RV64 defconfig"; "irqchip/riscv-rpmi-sysmsi: Add ACPI support". Board and device tree support got 30 commits. KVM and virtualisation received 19 patches. Work on Zfh, Zfhmin, Zicbom, Zicbop, Zicboz accounted for 10 commits.
50 New features & support30 Device tree / platform support19 KVM / Virtualisation10 ISA extensions6 Bug fixes6 Performance optimisations4 Interrupt controllers (AIA/APLIC/PLIC)3 Cleanup & refactoring
Notable Changes
RISC-V: KVM: add support for FWFT SBI extension (6b72fd1705, Clément Léger)
riscv: dts: spacemit: Add Ethernet support for Jupiter (and 2 more) (e32dc7a936, Vivian Wang)
riscv: Add __attribute_const__ to ffs()-family implementations (c51c26e687, Kees Cook)
riscv: defconfig: Enable MMP_PDMA support for SpacemiT K1 SoC (3df7ce0e43, Guodong Xu)
RISC-V: KVM: Add support for SBI_FWFT_POINTER_MASKING_PMLEN (6f576fc0ae, Samuel Holland)
RISC-V: Add defines for the SBI message proxy extension (508da38677, Anup Patel)
RISC-V: KVM: add support for SBI_FWFT_MISALIGNED_DELEG (bb053f816a, Clément Léger)
OpenSBI saw lighter activity with 10 commits from 3 contributors. The codebase got leaner: +196/-246. Most of the work came from Samuel Holland (6 of 10 commits, 60%). The interrupt subsystem got 1 patch of attention this month. On the mailing list, "lib: utils: Add cache flush library (2-patch series)" drew 17 replies.
2 New features & support1 Interrupt controllers (AIA/APLIC/PLIC)
Notable Changes
lib: sbi_list: Add a helper for reverse list iteration (64a38525e6, Samuel Holland)
GCC (RISC-V) had a solid month with 49 commits from 17 contributors. Paul-Antoine Arras was the most active contributor with 10 commits. New feature work included 21 commits: "fmv: c++: Add check_target_clone hook for filtering target_clone versions."; "RISC-V: Add missing define_insn_reservation to tt-ascalon-d8.md [PR121982]". Vector extension support moved forward with 16 commits. Compiler backend and code generation improvements accounted for 15 commits. ISA extension work spanned 9 commits, touching Zicsr. Worth reading: the "RISC-V: Allow VLS types using up to LMUL 8" thread attracted 21 responses on the mailing list.
21 New features & support16 Vector extension (RVV)15 Compiler backend / code generation9 ISA extensions7 Bug fixes4 Cleanup & refactoring3 Performance optimisations
Notable Changes
RISC-V: Add support for the XAndesvdot ISA extension. (and 6 more) (c4d5383b1d, Kuan-Lin Chen)
RISC-V: Add pattern for vector-scalar single widening floating-point sub (and 9 more) (e18285867e, Paul-Antoine Arras)
RISC-V: Combine vec_duplicate + vwaddu.vv to vwaddu.vx on GR2VR cost (and 2 more) (638320686c, Pan Li)
It was a busy month in LLVM (RISC-V) land, with 172 commits from 49 contributors. +92,122/-46,305 lines changed — a big diff. Craig Topper was the most active contributor with 49 commits. New feature work included 49 commits: "Revert "[TTI][RISCV] Add cost modelling for intrinsic vp.load.ff (#160470)""; "[ASan][RISCV] Teach AddressSanitizer to support indexed load/store. (#160443)". Code generation improvements dominated with 44 commits. Work on QC_E_LI, Zibi, Zicond accounted for 20 commits.
49 New features & support45 Cleanup & refactoring44 Compiler backend / code generation20 ISA extensions13 Bug fixes8 Performance optimisations5 Vector extension (RVV)
Notable Changes
[RISCV][CodeGen] Add CodeGen support of Zibi experimental extension (#146858) (27f8f9e1f1, Boyao Wang)
[RISCV] Add MC layer support for Andes XAndesVSIntH extension. (#159514) (d34f738562, Rux124)
[RISCV][MC] Add MC support of Zibi experimental extension (#127463) (a7521a81c4, Boyao Wang)
[RISCV] Implement MC support for Zvfofp8min extension (#157014) (e747223c03, Jim Lin)
[RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (#155747) (1debf23d7a, UmeshKalappa)
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386) (8fdae0c7da, Elvis Wang)
[RISCV][NFC] Add zeroext attribute to evl arguments in vp-vector-interleaved-access.ll test (b4a43b3bfa, Min-Yih Hsu)
[DAG] Add ISD::VECTOR_COMPRESS handling in computeKnownBits/ComputeNumSignBits (#159692) (d46998b1dd, Kavin Gnanapandithan)
[RISCV] Add helper method for detecting BEXTI or TH_TST is supported. NFC (#157915) (c6947dad53, Craig Topper)
[LLVM][MC][DecoderEmitter] Add support to specialize decoder per bitwidth (#154865) (dafffe262d, Rahul Joshi)
[GlobalISel] Add multi-way splitting support for wide scalar shifts. (#155353) (4829dedfa9, Amara Emerson)
[ASan][RISCV] Teach AddressSanitizer to support indexed load/store. (#160443) (d2c189bc73, Hank Chang)
[RISC-V] Add P-ext MC Support for Remaining Pair Operations (#159247) (dd92609fcc, Qihan Cai)
[RISCV] Implement computeKnownBitsForTargetNode for SHL_ADD (#159105) (7a098aecb6, Piotr Fusik)
Top Contributors
Author
Commits
Craig Topper
49
Luke Lau
14
Min-Yih Hsu
10
Philip Reames
9
Jim Lin
7
Sam Elliott
5
Matt Arsenault
5
Sergei Barannikov
5
Shaoce SUN
4
Piotr Fusik
4
glibc (RISC-V)
3
Commits
2
Contributors
7
Lines Added
3
Lines Removed
Minimal activity in glibc (RISC-V): 3 commits from 2 contributors. Adhemerval Zanella was the driving force, authoring 2 of 3 commits (66%). On the mailing list, "riscv: Add RVV implementation __strcpy_vector" drew 12 replies.
2 New features & support1 Bug fixes
Notable Changes
math: Add feclearexcept internal alias (2eb8836de7, Adhemerval Zanella)
math: Add fetestexcept internal alias (63ba1a1509, Adhemerval Zanella)
Fix RISC-V soft-float _FPU_SETCW for GCC 16 set-but-not-used warnings (273f80374a, Joseph Myers)
GDB (RISC-V) was quiet this month with 3 commits from 3 contributors.
1 New features & support
Notable Changes
This commit adds support for catching syscalls on riscv (52bb1ca383, Timur Golubovich)
gdb/riscv/record: remove possibility of recording an empty instruction (7fb4db4c63, Guinevere Larsen)
Use c-ctype.h (not safe-ctype.h) in gdb (15e11aac9c, Tom Tromey)
Top Contributors
Author
Commits
Timur Golubovich
1
Guinevere Larsen
1
Tom Tromey
1
U-Boot (RISC-V)
11
Commits
5
Contributors
180
Lines Added
950
Lines Removed
Not the busiest month for U-Boot (RISC-V): 11 commits from 5 contributors. A net deletion month (+180/-950) — always satisfying. Top contributor: E Shattow with 5 commits. Platform and DT work accounted for 5 commits. Extension support saw 2 commits covering Zaamo, Zalrsc.
5 Device tree / platform support2 ISA extensions2 New features & support2 Cleanup & refactoring
Notable Changes
riscv: Add a Zalrsc-only alternative for synchronization in start.S (a681cfecb4, Yao Zi)
riscv: Add Kconfig options to distinguish Zaamo and Zalrsc (fde7702c9b, Yao Zi)
riscv: dts: starfive: visionfive2 depend on SYS_CPU automatic dtsi inclusion (and 2 more) (b8732d30a4, E Shattow)
configs: starfive: Use visionfive2 DEVICE_TREE_INCLUDES dtsi named similar to defconfig (10fdc2735d, E Shattow)
board: microchip: icicle: rename all icicle files to generic (d141a41feb, Jamie Gibbons)
starfive: avoid NULL dereference in fdt_check_header() (686b48af6d, Heinrich Schuchardt)
arch/riscv: Remove unused macro in encoding.h (36d9587fa8, Greentime Hu)
dts: th1520: Switch to upstream devicetree (0d74bbfda3, Yao Zi)
Top Contributors
Author
Commits
E Shattow
5
Yao Zi
3
Greentime Hu
1
Jamie Gibbons
1
Heinrich Schuchardt
1
OpenOCD (RISC-V)
6
Commits
3
Contributors
106
Lines Added
80
Lines Removed
OpenOCD (RISC-V) saw lighter activity with 6 commits from 3 contributors. Most of the work came from Marc Schink (4 of 6 commits, 66%).
3 New features & support
Notable Changes
jtag/drivers/cmsis_dap: add new backend cmsis_dap_tcp (fcff4b712c, Brian Kuschak)
adapter: Rework parallel port driver (and 2 more) (7bc74de62d, Marc Schink)
doc: drop incorrect lack of namespaces in Jim Tcl (db79156fd5, Antonio Borneo)
flash/nor/stm32l4x: Change 'option_read' output (20ca4f4bee, Marc Schink)
Top Contributors
Author
Commits
Marc Schink
4
Antonio Borneo
1
Brian Kuschak
1
OpenBLAS (RISC-V)
9
Commits
3
Contributors
2912
Lines Added
485
Lines Removed
OpenBLAS (RISC-V) saw lighter activity with 9 commits from 3 contributors. Top contributor: Chip Kerchner with 4 commits. RVV work continued with 5 commits touching vector-related code. 4 commits targeted performance improvements.
5 Vector extension (RVV)4 Performance optimisations3 New features & support1 Bug fixes1 Cleanup & refactoring
Notable Changes
Optimize RISC-V RVV omatcopy_ct implementation with advanced vectorization (bd45b82ed0, Dayuxiaoshui)