The RISC-V upstream saw 286 commits across 13 projects this October. The most active projects were LLVM (RISC-V) (106), Linux Kernel (RISC-V) (49), QEMU (RISC-V) (48). Extension support continued to broaden, with work on QC_SETWMI, QC_SHLADD, Zaamo, Zacas, Zalrsc, Zdinx, Zfinx, Zvfhmin. Virtualisation saw 7 KVM-related patches. Most-discussed mailing list thread: "riscv: Add RVV memset via multiarch/IFUNC" (glibc (RISC-V), 17 replies).
RISC-V International
The spec repos saw 24 commits this month, led by ISA Manual with 20 commits.
Spec Repository Activity
Repository
Commits
Contributors
ISA Manual
20
10
ELF psABI
3
2
SBI Spec
1
1
Community Buzz (r/RISCV)
The most popular posts on
r/RISCV this month,
ranked by upvotes.
Linux Kernel (RISC-V) saw healthy activity with 49 commits from 26 contributors. Samuel Holland was the most active contributor with 7 commits. New feature work included 17 commits: "riscv: dts: thead: Add PWM fan and thermal control"; "riscv: dts: thead: Add PWM controller node". Board and device tree support got 17 commits. The interrupt subsystem got 7 patches of attention this month. Bug fixes accounted for 6 commits (12%).
17 New features & support17 Device tree / platform support7 Interrupt controllers (AIA/APLIC/PLIC)6 Bug fixes3 KVM / Virtualisation3 ISA extensions2 Vector extension (RVV)1 Security & memory safety fixes1 Cleanup & refactoring
Notable Changes
irqchip/sifive-plic: Add support for UltraRISC DP1000 PLIC (539d147ef6, Charles Mirabile)
irqchip/riscv-imsic: Inline imsic_vector_from_local_id() (and 2 more) (3a16b05384, Samuel Holland)
riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs (16eb4e02a6, Drew Fustini)
OpenSBI kept moving with 24 commits from 8 contributors. Leading the charge was Nick Hu with 11 commits. New feature work included 17 commits: "lib: utils/suspend: Add SiFive SMC0 driver"; "lib: sbi: Add system_resume callback for restoring the system". The interrupt subsystem got 1 patch of attention this month.
17 New features & support2 Device tree / platform support1 Interrupt controllers (AIA/APLIC/PLIC)
QEMU (RISC-V) saw healthy activity with 48 commits from 19 contributors. Top contributor: Philippe Mathieu-Daudé with 18 commits. Bug fixes accounted for 10 commits (20%). The KVM subsystem saw 4 patches this month.
10 Bug fixes5 New features & support4 KVM / Virtualisation4 ISA extensions3 Vector extension (RVV)1 Cleanup & refactoring1 Device tree / platform support
Notable Changes
target/riscv: Introduce mo_endian_env() helper (and 12 more) (d652720ecc, Philippe Mathieu-Daudé)
microchip icicle: Enable PCS on Cadence Ethernet (cdbb7c3fa6, Guenter Roeck)
target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64 (and 2 more) (81d1885dcc, Max Chou)
target/riscv: Use 32 bits for misa extensions (89e1cd7363, Anton Johansson)
target/riscv: implement MonitorDef HMP API (e06d209aa6, Daniel Henrique Barboza)
accel/kvm: Introduce KvmPutState enum (665a8035b7, Philippe Mathieu-Daudé)
target/riscv/kvm: Replace legacy cpu_physical_memory_read/write() calls (b4c93258a9, Philippe Mathieu-Daudé)
target/riscv/kvm: Use riscv_cpu_is_32bit() when handling SBI_DBCN reg (c69fc80035, Philippe Mathieu-Daudé)
hw/riscv: Correct mmu-type property of sifive_u harts in device tree (e41139eaad, Zejun Zhao)
target/riscv/monitor: Replace legacy cpu_physical_memory_read() call (d936261844, Philippe Mathieu-Daudé)
qom: remove redundant typedef when use OBJECT_DECLARE_SIMPLE_TYPE (b12c1b3724, Nguyen Dinh Phi)
accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx (482869ca84, Philippe Mathieu-Daudé)
target/riscv: Fix endianness swap on compressed instructions (b25133d38f, vhaudiquet)
target/riscv/kvm: fix env->priv setting in reset_regs_csr() (2a21cbee47, Daniel Henrique Barboza)
GCC (RISC-V) saw moderate activity with 28 commits from 12 contributors. Top contributor: Jeff Law with 9 commits. Bug fixes accounted for 9 commits (32%). Compiler backend and code generation improvements accounted for 8 commits. RVV work continued with 6 commits touching vector-related code.
9 Bug fixes8 Compiler backend / code generation6 Vector extension (RVV)4 New features & support1 ISA extensions1 Cleanup & refactoring1 Performance optimisations
Notable Changes
[RISC-V][PR target/120674] Avoid division by zero in dwarf emitter when vector is not enabled (a92369a6be, Jeff Law)
[PATCH v2] RISC-V: avlprop: Scale AVL by subreg ratio [PR122445]. (bce897412c, Robin Dapp)
Top Contributors
Author
Commits
Jeff Law
9
Robin Dapp
3
Kito Cheng
3
Pan Li
3
Zhongyao Chen
2
Raphael Moreira Zinsly
2
Andrew Pinski
1
Kuan-Lin Chen
1
Shreya Munnangi
1
Bohan Lei
1
LLVM (RISC-V)
106
Commits
29
Contributors
67927
Lines Added
6524
Lines Removed
Plenty of action in LLVM (RISC-V) this month: 106 commits from 29 contributors. That's +67,927/-6,524 lines of churn. Top contributor: Craig Topper with 51 commits. Code housekeeping was a significant theme at 46 commits (43%). Code generation improvements dominated with 40 commits. New feature work included 33 commits: "[RISCV] Support P extension ABSW instruction. (#165047)"; "[RISCV][GISel] Support select vector load intrinsics (#160720)". ISA extension work spanned 27 commits, touching QC_SETWMI, QC_SHLADD, Zaamo, Zacas, Zalrsc, Zdinx.
46 Cleanup & refactoring40 Compiler backend / code generation33 New features & support27 ISA extensions8 Vector extension (RVV)8 Bug fixes2 Performance optimisations
Notable Changes
[RISCV][MC] Introduce XSfvfexp* and XSfvfbfexpa* extensions and their MC supports (#164349) (90bc75043c, Min-Yih Hsu)
[RISCV] Add a new subtarget feature for throttled FP64 vector performance (#162399) (69f913821d, Min-Yih Hsu)
[RISCV] Add commutative support for Qualcomm uC Xqcics extension (#161328) (1098a5cefd, quic_hchandel)
[RISCV] Add an explicit i32 to QC_SETWMI pattern to reduce RISCVGenDAGISel.inc. NFC (#162720) (e02c645f90, Craig Topper)
[RISCV][NFC] Avoid iteration and division while selecting SHXADD instructions (#158851) (3a3a524f54, Piotr Fusik)
[RISCV] Add helper function getVecPolicyOpNum in RISCVInsertVSETVLI.cpp. NFC. (#161476) (8b9e208448, Jim Lin)
[RISCV][GISel] Add manual isel for s8/s16/s32 load/store for the GPR bank. (#161995) (bd1561d5f1, Craig Topper)
Top Contributors
Author
Commits
Craig Topper
51
Jim Lin
7
Min-Yih Hsu
6
Brandon Wu
5
Kazu Hirata
4
Philip Reames
3
Sam Elliott
3
Jianjian Guan
3
slachowsky
2
Jakub Kuderski
2
glibc (RISC-V)
6
Commits
2
Contributors
27
Lines Added
23
Lines Removed
A quieter month for glibc (RISC-V), with 6 commits from 2 contributors. On the mailing list, "riscv: Add RVV memset via multiarch/IFUNC" drew 17 replies.
2 Bug fixes2 New features & support1 Compiler backend / code generation1 Cleanup & refactoring
Notable Changes
Implement C23 memset_explicit (bug 32378) (0f201f4a81, Joseph Myers)
riscv: memcpy_noalignment: Reorder to store via a3, then bump a3 (and 2 more) (09a94c86ca, Yao Zihong)
Implement C23 memalignment (ea18d5a4c2, Joseph Myers)
Rename uimaxabs to umaxabs (bug 33325) (096fcdc0a5, Joseph Myers)
Minimal activity in Binutils (RISC-V): 2 commits. Most of the work came from Jan Beulich (2 of 2 commits, 100%).
Notable Changes
bfd: move sec_info from ELF to general section struct (eb92a17c47, Jan Beulich)
bfd: simplify _bfd_merged_section_offset() interface (f2dbe10f66, Jan Beulich)
Top Contributors
Author
Commits
Jan Beulich
2
GDB (RISC-V)
2
Commits
2
Contributors
144
Lines Added
342
Lines Removed
GDB (RISC-V) was quiet this month with 2 commits from 2 contributors. The codebase got leaner: +144/-342. Optimisation efforts accounted for 1 commit.
1 Performance optimisations
Notable Changes
Rewrote riscv-canonicalize-gen.py using xml file (321ac819c4, Timur Golubovich)
gdb/record: Speeding up recording in RISC-V (bef948d551, timurgol007)
Top Contributors
Author
Commits
timurgol007
1
Timur Golubovich
1
U-Boot (RISC-V)
6
Commits
4
Contributors
66
Lines Added
1036
Lines Removed
A quieter month for U-Boot (RISC-V), with 6 commits from 4 contributors. Notably, more code was removed than added (+66/-1,036). Extension support saw 1 commit covering Zalrsc.
3 New features & support1 ISA extensions1 Device tree / platform support
Notable Changes
board: starfive: visionfive2: Add Milk-V Mars CM and Mars CM Lite selection by product_id (6674ffb51b, E Shattow)
board: starfive: Add initial Milk-V Mars CM and Mars CM Lite user documentation (e1c05c0069, E Shattow)
Revert "riscv: Add a Zalrsc-only alternative for synchronization in start.S" (e6646b35f4, Yao Zi)
riscv: dts: starfive: prune redundant jh7110 overrides (e599023f31, E Shattow)
sunxi: switch the Allwinner T113 SoC to OF_UPSTREAM (15e158ccd9, Andre Przywara)
spl: split spl_board_fixups to arch/board specific (16ffcff028, Anshul Dalal)