November brought 295 commits across 13 projects in the RISC-V stack. The most active projects were LLVM (RISC-V) (118), Linux Kernel (RISC-V) (65), GCC (RISC-V) (29). Extension support work touched Smpmpmt, Zicbop, Zicond, Zvbb. Virtualisation saw 10 KVM-related patches. Most-discussed mailing list thread: "Initial ESWIN/EIC7700 support" (OpenSBI, 9 replies).
RISC-V International
The spec repos saw 17 commits this month, led by ELF psABI with 9 commits.
Spec Repository Activity
Repository
Commits
Contributors
ELF psABI
9
4
ISA Manual
8
6
Community Buzz (r/RISCV)
The most popular posts on
r/RISCV this month,
ranked by upvotes.
I have it! <3(223 pts, 19 comments, u/IngwiePhoenix)
Linux Kernel (RISC-V) had a solid month with 65 commits from 35 contributors. Top contributor: Vivian Wang with 5 commits. New feature work included 38 commits: "riscv: dts: starfive: add Orange Pi RV"; "riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree". Platform and DT work accounted for 25 commits. ISA extension work spanned 14 commits, touching Zicbop. Virtualisation work accounted for 9 patches, continuing to mature RISC-V KVM support.
38 New features & support25 Device tree / platform support14 ISA extensions9 KVM / Virtualisation5 Bug fixes2 Interrupt controllers (AIA/APLIC/PLIC)1 Vector extension (RVV)1 Cleanup & refactoring1 Performance optimisations
Notable Changes
RISC-V: KVM: Add SBI MPXY extension support for Guest (and 2 more) (7050f1d79f, Anup Patel)
riscv: add RISC-V Svrsw60t59b extension support (59f6acb4be, Chunyan Zhang)
riscv: ptrace: Optimize the allocation of vector regset (6efb1a9462, Yong-Xuan Wang)
riscv: mm: add userfaultfd write-protect support (c64da3950c, Chunyan Zhang)
riscv: mm: add soft-dirty page tracking support (2a3ebad4db, Chunyan Zhang)
riscv: dts: sophgo: Add USB support for cv18xx (e307248a3c, Longbin Li)
riscv: Add Anlogic SoC famly Kconfig support (9c96219602, Junhui Liu)
riscv: Add ISA extension parsing for Zalasr (c9651fbc60, Xu Lu)
riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree (and 3 more) (ae264ae124, Hal Feng)
irqchip/riscv-intc: Add missing free() callback in riscv_intc_domain_ops (14473a1f88, Nick Hu)
riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 (and 3 more) (af5eb17ff8, Zixian Zeng)
riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV Fire (1088d49b62, Conor Dooley)
KVM: riscv: Support enabling dirty log gradually in small chunks (df60cb2e67, Dong Yang)
A steady month for OpenSBI with 17 commits from 5 contributors. Leading the charge was Yu-Chien Peter Lin with 8 commits. New feature work included 6 commits: "lib: utils/timer: mtimer: add MIPS P8700 compatible"; "lib: utils/ipi: mswi: add MIPS P8700 compatible". The interrupt subsystem got 4 patches of attention this month. Optimisation efforts accounted for 1 commit.
6 New features & support4 Interrupt controllers (AIA/APLIC/PLIC)2 ISA extensions1 Performance optimisations1 Device tree / platform support
GCC (RISC-V) kept moving with 29 commits from 12 contributors. Leading the charge was Jeff Law with 8 commits. New feature work included 11 commits: "RISC-V: Support --with-cpu"; "RISC-V: Add SpacemiT extension xsmtvdot". ISA extension work spanned 7 commits, touching Zvbb. Bug fixes accounted for 4 commits (13%).
11 New features & support7 ISA extensions4 Bug fixes3 Compiler backend / code generation2 Vector extension (RVV)1 Cleanup & refactoring
RISC-V: Add SpacemiT extension xsmtvdot (b028abd092, Mark Zhuang)
[RISC-V] Expose sign extension for 32 bit rotates by constant values on rv64 (27ddde739d, Jeff Law)
RISC-V: Add RTL pass to combine cm.popret with zero return value (c738d4ef52, Kito Cheng)
[RISC-V] Add cpu and tuning structures for spacemit-x60 design (3dc4bcb0cd, Austin Law)
RISC-V: Add Andes 45 series pipeline description. (and 4 more) (3d3a3e20a0, Kuan-Lin Chen)
RISC-V: Add flag to adjust mem inlining threshold (76c7c5dc5d, Edwin Lu)
RISC-V: Add BF VLS modes and document iterators. (3b4c34e3e4, Robin Dapp)
[RISC-V][PR 121136] Improve various tests which only need to examine upper bits in a GPR (5e93ab0da7, Your Name)
[PATCH v1] RISC-V: Fix missed zero extend for unsigned scalar SAT_TRUNC [PR122692] (8615c855fa, Pan Li)
[RISC-V] Ignore useless zero-initialization in conditional move sequence costing (d277d4e374, Jeff Law)
[RISC-V] Reorder ready queue slightly to avoid unnecessary vsetvl instructions (6363288965, Jeff Law)
RISC-V: RISC-V: Combine vec_duplicate + vwmaccu.vv to vwmaccu.vx on GR2VR cost (94e605a808, Pan Li)
RISC-V: Support --with-cpu (5be645aae5, Charlie Jenkins)
RISC-V: Fix the ABI of empty unions and zero length array in struct (0d0028f8df, Kito Cheng)
Top Contributors
Author
Commits
Jeff Law
8
Kuan-Lin Chen
5
Robin Dapp
3
Pan Li
3
Mark Zhuang
2
Kito Cheng
2
Jakub Jelinek
1
Jim Lin
1
Charlie Jenkins
1
Edwin Lu
1
LLVM (RISC-V)
118
Commits
39
Contributors
41682
Lines Added
126827
Lines Removed
It was a busy month in LLVM (RISC-V) land, with 118 commits from 39 contributors. A net deletion month (+41,682/-126,827) — always satisfying. Leading the charge was Craig Topper with 28 commits. New feature work included 43 commits: "[RISCV] Intrinsic Support for XCVelw (#129168)"; "[LLD] Add support for statically resolved vendor-specific RISCV relocations. (#169273)". Backend and code generation work was the biggest theme at 33 commits. The vector extension (RVV) saw 18 commits of continued development.
43 New features & support33 Compiler backend / code generation21 Cleanup & refactoring18 Vector extension (RVV)18 ISA extensions10 Bug fixes4 Performance optimisations
Notable Changes
[RISCV][llvm] Support BUILD_VECTOR codegen for P extension (#169083) (d889b97f2b, Brandon Wu)
[DAGCombiner] Don't optimize insert_vector_elt into shuffle if implicit truncation exists (#169022) (3fec26e329, Hongyu Chen)
[RISCV] Incorporate scalar addends to extend vector multiply accumulate chains (#168660) (39d4dfbe55, Ryan Buchner)
[LLD] Add support for statically resolved vendor-specific RISCV relocations. (#169273) (0c6d7a4018, Owen Anderson)
[RISCV] Add short forward branch support for `lui`, `qc.li`, and `qc.e.li` (#167481) (b1343e33c7, quic_hchandel)
[RISCV] Optimize (and (icmp x, 0, neq), (icmp y, 0, neq)) utilizing zicond extension (856ef9605b, Ryan Buchner)
[RISCV][GISel] Support select indexed vector load store intrinsics (#165876) (c63cb50080, Jianjian Guan)
[AArch64][GlobalISel] Added support for hadd family of intrinsics (#163985) (4353845838, Joshua Rodriguez)
[llvm][RISCV] Do not assume V extension on seeing vector type. (#166994) (6d516c6e28, Chenguang Wang)
[RISCV] Add short forward branch support for `mul` instruction (#166300) (04619db16b, quic_hchandel)
[RISCV][llvm] Preliminary P extension codegen support (#162668) (dfdc69b4c2, Brandon Wu)
[IR] Add new function attribute nocreateundeforpoison (#164809) (f037f41350, Jay Foad)
[RISCV] Add an option to enable CFIInstrInserter. (#164477) (6886d4945f, Mikhail Gudim)
Reland "[clang] Refactor option-related code from clangDriver into new clangOptions library" (#167374) (f63d33da0a, Naveen Seth Hanig)
Revert "[clang] Refactor option-related code from clangDriver into new clangOptions library" (#167348) (6bad2d139b, Naveen Seth Hanig)
Top Contributors
Author
Commits
Craig Topper
28
Brandon Wu
11
Matt Arsenault
9
Luke Lau
8
Piotr Fusik
6
Mikhail R. Gadelha
5
Mikhail Gudim
4
Alex Bradbury
4
Hongyu Chen
3
Naveen Seth Hanig
3
glibc (RISC-V)
11
Commits
5
Contributors
160
Lines Added
192
Lines Removed
A quieter month for glibc (RISC-V), with 11 commits from 5 contributors. The codebase got leaner: +160/-192. Adhemerval Zanella was the most active contributor with 6 commits. RVV work continued with 1 commit touching vector-related code.
5 New features & support1 Vector extension (RVV)1 Bug fixes
Notable Changes
riscv: Add vector registers to __SYSCALL_CLOBBERS (47975914fb, Peter Bergner)
linux: Add mseal syscall support (3d52fd274e, Adhemerval Zanella)
malloc: add free_sized and free_aligned_sized from C23 (56549264d1, Justin King)
A quieter month for Rust (RISC-V), with 7 commits from 4 contributors. Tamir Duberstein was the most active contributor with 4 commits. New feature work included 6 commits: "rustc_target: introduce Os"; "rustc_target: introduce Env".
6 New features & support
Notable Changes
Implement the MCP 932: Promote riscv64a23-unknown-linux-gnu to Tier 2 without host tools (1af9b63c7b, Zhongyao Chen)
Add default sanitizers to TargetOptions (e207006ad3, Paul Kirth)
rustc_target: introduce Os (and 3 more) (fcf6809b05, Tamir Duberstein)
Mark riscv64gc-unknown-linux-musl as tier 2 target (fd1852f5f3, Mateusz Mikuła)
Top Contributors
Author
Commits
Tamir Duberstein
4
Mateusz Mikuła
1
Paul Kirth
1
Zhongyao Chen
1
OpenOCD (RISC-V)
25
Commits
10
Contributors
19042
Lines Added
8893
Lines Removed
OpenOCD (RISC-V) kept moving with 25 commits from 10 contributors. +19,042/-8,893 lines changed — a big diff. Leading the charge was Antonio Borneo with 8 commits. Bug fixes accounted for 7 commits (28%). Virtualisation work accounted for 1 patch, continuing to mature RISC-V KVM support.
7 Bug fixes4 New features & support1 Security & memory safety fixes1 KVM / Virtualisation1 ISA extensions1 Cleanup & refactoring
Notable Changes
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files (56141bb349, Bernhard Rosenkränzer)
target/riscv: fix SV57 translation for kernel address space (12ab80ab45, Parshintsev Anatoly)
jtag/drivers/bcm2835gpio: Support all 54 GPIO pins (0021ee2f5d, Vincent Fazio)
flash/nor/stm32lx: Add 'option_load' command (a1c7cd4fef, Marc Schink)
target: riscv-011: don't change 'debug_level' during target polling (da96d3d41b, Antonio Borneo)
target/riscv: fix progbuf memory writes in case last write is busy (4e78563a00, Evgeniy Naydanov)
target/riscv: fix get mode filed for vsatp and hgatp (and 4 more) (18734bcf95, Tomas Vanek)
target/riscv: improve error messaging in case `sbasize` is zero (f5ce311103, Sriram Shanmuga)
target: semihosting: refresh URI to semihosting documentation (23fc7e9c96, Antonio Borneo)
target: riscv: move the SMP commands under riscv (and 4 more) (52ac91a73e, Antonio Borneo)
doc: import document changes relevant to riscv code update (b4fb5a7baa, Tomas Vanek)
target, flash: utility for riscv repeat_read command (a0eac82708, Tomas Vanek)
target: riscv: Sync with the RISC-V fork (5754aebc49, Bernhard Rosenkränzer)
doc: riscv: minor fixes in openocd.texi (2913dff98a, Tomas Vanek)
Top Contributors
Author
Commits
Antonio Borneo
8
Tomas Vanek
8
Bernhard Rosenkränzer
2
Marc Schink
1
Vincent Fazio
1
Evgeniy Naydanov
1
Parshintsev Anatoly
1
Sriram Shanmuga
1
Erhan Kurubas
1
Daniel Anselmi
1
OpenBLAS (RISC-V)
3
Commits
2
Contributors
232
Lines Added
220
Lines Removed
Minimal activity in OpenBLAS (RISC-V): 3 commits from 2 contributors. Most of the work came from Chip Kerchner (2 of 3 commits, 66%). Performance work included 1 commit.
1 Performance optimisations
Notable Changes
Optimize ZROT_RVV for the unit-stride case (inc_x = inc_y = 1) (98a8230dee, daichengrong)
Prevent possible conversion from bfloat16 to __bf16. (edf2e5900c, Chip Kerchner)
Missing one gemv conversion. (00a7336fc9, Chip Kerchner)
Top Contributors
Author
Commits
Chip Kerchner
2
daichengrong
1
Eigen (RISC-V)
1
Commits
1
Contributors
6568
Lines Added
0
Lines Removed
Eigen (RISC-V) had exactly one commit this month. The vector extension (RVV) saw 1 commit of continued development.
1 Vector extension (RVV)1 ISA extensions1 New features & support
Notable Changes
This patch adds support for RISCV's vector extension RVV1.0. (49623d0c4e, Chip Kerchner)
Top Contributors
Author
Commits
Chip Kerchner
1
Linux Kernel Docs & DT (RISC-V)
8
Commits
7
Contributors
48
Lines Added
0
Lines Removed
A quieter month for Linux Kernel Docs & DT (RISC-V), with 8 commits from 7 contributors. New feature work included 8 commits: "dt-bindings: riscv: starfive: add xunlong,orangepi-rv"; "dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board". Board and device tree support got 8 commits.
8 New features & support8 Device tree / platform support2 ISA extensions