In December 2025, the RISC-V ecosystem saw 256 commits across 12 projects. The most active projects were LLVM (RISC-V) (127), OpenSBI (40), GCC (RISC-V) (31). The extension landscape saw work on QC_EXTU, QC_SETWMI, Zfinx, Zicond, Zifencei, Zihintntl, Zvfh. Most-discussed mailing list thread: "riscv: Add RVV memset for both multiarch and non-multiarch builds" (glibc (RISC-V), 10 replies).
RISC-V International
The spec repos saw 74 commits this month, led by ISA Manual with 72 commits.
Spec Repository Activity
Repository
Commits
Contributors
ISA Manual
72
19
ELF psABI
2
1
Community Buzz (r/RISCV)
The most popular posts on
r/RISCV this month,
ranked by upvotes.
A steady month for Linux Kernel (RISC-V) with 25 commits from 16 contributors. Platform and DT work accounted for 10 commits.
10 Device tree / platform support5 New features & support3 ISA extensions3 Bug fixes2 Interrupt controllers (AIA/APLIC/PLIC)1 Performance optimisations
Notable Changes
riscv: Add SBI debug trigger extension and function ids (5efaf92da4, Himanshu Chauhan)
riscv: add ISA extension parsing for Zilsd and Zclsd (3f0cbfb8a1, Pincheng Wang)
irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit (f48b4bd091, Nick Hu)
lib/crypto: riscv: Depend on RISCV_EFFICIENT_VECTOR_UNALIGNED_ACCESS (1cd5bb6e9e, Eric Biggers)
riscv: hwprobe: export Zilsd and Zclsd ISA extensions (6118ebed3b, Pincheng Wang)
riscv: dts: spacemit: Add a PCIe regulator (73a6c811fa, Alex Elder)
riscv: mm: use xchg() on non-atomic_long_t variables, not atomic_long_xchg() (and 2 more) (e0e51a0de0, Paul Walmsley)
riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board (4297ddbf1d, E Shattow)
riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter (and 2 more) (7d307daa12, Javier Martinez Canillas)
riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board (7c9a5fd6bb, E Shattow)
riscv: boot: Always make Image from vmlinux, not vmlinux.unstripped (66562b66dc, Vivian Wang)
riscv/atomic.h: use RISCV_FULL_BARRIER in _arch_atomic* function. (f02dd25472, Zongmin Zhou)
irqchip/riscv-aplic: Preserve APLIC states across suspend/resume (95a8ddde36, Nick Hu)
riscv: fix KUnit test_kprobes crash when building with Clang (641ecc8900, Jiakai Xu)
riscv: dts: microchip: convert clock and reset to use syscon (26535e8444, Conor Dooley)
A productive month for OpenSBI with 40 commits from 14 contributors. Top contributor: Anup Patel with 8 commits. New feature work included 12 commits: "platform: generic: eswin: Add shutdown/reboot support for Hifive Premier P550"; "lib: utils/serial: Support multiple UART8250 devices". Bug fixes accounted for 6 commits (15%). 2 commits targeted performance improvements.
12 New features & support6 Bug fixes2 Performance optimisations1 ISA extensions1 Device tree / platform support
Notable Changes
platform: generic: eswin: Add shutdown/reboot support for Hifive Premier P550 (73183a60ab, Bo Gan)
A quieter month for QEMU (RISC-V), with 8 commits from 2 contributors. Paolo Bonzini dominated with 7/8 commits (87%).
Notable Changes
hw/riscv: Treat kernel_start_addr as vaddr (ceaaeb2ad9, Anton Johansson)
include: move hw/sysbus.h to hw/core/ (and 6 more) (c755f3b959, Paolo Bonzini)
Top Contributors
Author
Commits
Paolo Bonzini
7
Anton Johansson
1
GCC (RISC-V)
31
Commits
9
Contributors
2803
Lines Added
775
Lines Removed
GCC (RISC-V) saw moderate activity with 31 commits from 9 contributors. Robin Dapp was the most active contributor with 13 commits. Vector extension support moved forward with 7 commits. New feature work included 7 commits: "[committed][RISC-V][PR target/123274] Add missing condition in usmul3 pattern"; "RISC-V: Add VLS modes to autovec iterators.". Compiler backend and code generation improvements accounted for 6 commits.
7 Vector extension (RVV)7 New features & support6 Compiler backend / code generation5 Cleanup & refactoring3 Bug fixes2 ISA extensions
Notable Changes
[PATCH][PR target/122942] RISC-V: Add zifencei extension to the rva23s64 and rvb23s64 profiles [PR122942] (976be4e014, Peter Bergner)
[committed][RISC-V][PR target/123274] Add missing condition in usmul3 pattern (758876f023, Jeff Law)
RISC-V: Remove unused placeholder_p parameter from add_function (24a1085072, Kito Cheng)
RISC-V: vsetvl: Add null check for fault-first loop [PR122652]. (b2d0abfcd5, Robin Dapp)
doc, riscv: Clean up RISC-V extensions documentation (7bf897e7c4, Sandra Loosemore)
[RISC-V][V2] Improve spill code for RVV slightly to fix regressions after recent changes (799fecc5f3, Jeff Law)
[RISC-V][PR target/123278] Handle BF/HF modes in Andes 45 series pipeline description (1444974955, Jeff Law)
RISC-V: Combine vec_duplicate + vmsleu.vv to vmsleu.vx on GR2VR cost (and 2 more) (678d0e0350, Pan Li)
RISC-V: Fix overflow check in interleave pattern [PR122970]. (and 11 more) (d4e6fc510f, Robin Dapp)
[RISC-V][PR target/123318] Use a Pmode temporary for output of auipc (7274c781e8, Jeff Law)
[RISC-V][PATCH] Adjust clmul latency in Spacemit X60 scheduler model (fa80b39721, Milan Tripkovic)
doc, riscv: Clean up documentation of RISC-V options [PR122243] (2bd7beba81, Sandra Loosemore)
[RISC-V][PR target/123283] Wrap naked REG operands with a USE. (4b618758b2, Jeff Law)
Fix various RISC-V testsuite regressions after volatile patch (09ed6a3d8d, Jeff Law)
[riscv] avoid auipc overflow with large offsets [PR91420] (fb8a9da75a, Alexandre Oliva)
Top Contributors
Author
Commits
Robin Dapp
13
Jeff Law
6
Sandra Loosemore
4
Pan Li
3
Milan Tripkovic
1
Jerry Zhang Jian
1
Alexandre Oliva
1
Kito Cheng
1
Peter Bergner
1
LLVM (RISC-V)
127
Commits
34
Contributors
33074
Lines Added
9841
Lines Removed
LLVM (RISC-V) saw heavy activity with 127 commits from 34 contributors. A hefty +33,074/-9,841 line diff. Leading the charge was Craig Topper with 44 commits. Backend and code generation work was the biggest theme at 38 commits. New feature work included 36 commits: "[RISCV] Add regalloc hints for BSETI/BEXTI (#173964)"; "[RISCV] Add regalloc hints for QC_EXTU (#173953)". Work on QC_EXTU, QC_SETWMI, Zfinx, Zicond, Zvfh accounted for 30 commits.
38 Compiler backend / code generation36 New features & support32 Cleanup & refactoring30 ISA extensions13 Bug fixes10 Vector extension (RVV)1 Performance optimisations
Notable Changes
[RISCV] Introduce new AND combine to expose additional load narrowing opportunities (#170483) (3ce0552d1a, Alex Bradbury)
[RISCV] Add short forward branch support for `lb`, `lbu`, `lh`, `lhu`, `lw`, `lwu` and `ld` (#170829) (5bf5657a97, quic_hchandel)
[RISCV] Add short forward branch support for `qc.e.lb(u)`, `qc.e.lh(u)` and `qc.e.lw` (#172629) (8a0cdb88f9, quic_hchandel)
[RISCV][llvm] Support PSRA, PSRAI, PSRL, PSRLI codegen for P extension (#171460) (794551dbff, Brandon Wu)
[RISCV][llvm] Support VFADD, VFSUB, VFMUL codegen for Zvfbfa (#170612) (e48d49fd6d, Brandon Wu)
[RISCV] Enable use of PACK in RISCVMatInt with P extension. (#172760) (94e03a7894, Craig Topper)
[RISCV] Implement conditional Zca implies C extension rule (#172860) (fc69c804db, Jerry Zhang Jian)
[RISC-V] Add schedule information for Qualcomm extensions (#172601) (f8ab74f25e, Venkata Ramanaiah Nalamothu)
[RISCV] Implement Clang Builtins for XAndesPerf Extension (#147018) (fcf762c6ec, Jim Lin)
[RISCV][llvm] Support fminimum, fmaximum, fminnum, fmaxnum, fminimumnum, fmaximumnum codegen for zvfbfa (#171794) (1e90a273fe, Brandon Wu)
[RISCV] Enable PACK isel patterns for P extension. (#173064) (418241db24, Craig Topper)
[llvm][RISCV] Support mulh for P extension codegen (#171581) (ef927ae263, Brandon Wu)
[RISCV] Custom legalize i32 saddo/ssubo on RV64 to return a sign extended value for the data result. (#172112) (ffaa6f23fd, Craig Topper)
[RISCV][llvm] Support PSLL codegen for P extension (#170074) (af4098b45a, Brandon Wu)
[RISCV][GISel] Support select G_EXTRACT_SUBVECTOR (#169789) (e66e8aac6e, Jianjian Guan)
Top Contributors
Author
Commits
Craig Topper
44
Brandon Wu
11
Sudharsan Veeravalli
10
Jim Lin
6
Luke Lau
5
Jianjian Guan
4
Alex Bradbury
4
Pengcheng Wang
4
Min-Yih Hsu
3
Frederik Harwath
3
glibc (RISC-V)
3
Commits
3
Contributors
217
Lines Added
6
Lines Removed
A light month for glibc (RISC-V) with 3 commits from 3 contributors. RVV work continued with 1 commit touching vector-related code. Worth reading: the "riscv: Add RVV memset for both multiarch and non-multiarch builds" thread attracted 10 responses on the mailing list.
2 New features & support1 Vector extension (RVV)
Notable Changes
riscv: Add RVV memset for both multiarch and non-multiarch builds (0b8a996f44, Yao Zihong)
Not the busiest month for OpenOCD (RISC-V): 6 commits from 4 contributors.
2 New features & support1 Cleanup & refactoring
Notable Changes
doc: add hpm_xpi flash driver description (e440b0648f, Ryan QIAN)
flash/nor/bl602: add bl602 flash driver (df2eb07086, Marek Kraus)
board/ti_*.cfg: Move TI evm platform configurations to board/ti folder (13a082fc7e, Nishanth Menon)
target/riscv: tcl/target: move the WA for GD32VF103 to Tcl (21e345a2f7, Evgeniy Naydanov)
board/ti: Rename _swd_native.cfg as -self-hosted.cfg (6a5e4dc2a3, Nishanth Menon)
tcl/target: Move TI targets to ti folder (2f8ddc0835, Nishanth Menon)
Top Contributors
Author
Commits
Nishanth Menon
3
Marek Kraus
1
Evgeniy Naydanov
1
Ryan QIAN
1
Eigen (RISC-V)
4
Commits
2
Contributors
994
Lines Added
227
Lines Removed
Eigen (RISC-V) was quiet this month with 4 commits from 2 contributors. Most of the work came from Chip Kerchner (3 of 4 commits, 75%). Vector extension support moved forward with 3 commits.
3 Vector extension (RVV)2 Bug fixes1 New features & support
Notable Changes
Add basic support for packetmath for BF16 RVV (4f14da11d9, Chip Kerchner)
Vectorize tan(x) (75bcd155c4, Rasmus Munk Larsen)
Fix FP16 for RVV so that it will compile for gcc (26fe567dd2, Chip Kerchner)
Fix naming of predux_half for RVV when LMUL > 1 (8cdc0fa67d, Chip Kerchner)
Top Contributors
Author
Commits
Chip Kerchner
3
Rasmus Munk Larsen
1
Linux Kernel Docs & DT (RISC-V)
2
Commits
2
Contributors
37
Lines Added
0
Lines Removed
Minimal activity in Linux Kernel Docs & DT (RISC-V): 2 commits from 2 contributors.
2 Device tree / platform support1 ISA extensions1 New features & support