With 356 commits across 12 projects, January was a solid month for RISC-V upstream development. LLVM (RISC-V) led with 189 commits (53%). Also active: Linux Kernel (RISC-V) (85), QEMU (RISC-V) (32), GCC (RISC-V) (19). Software support advanced for QC_EXTU, QC_E_ADDAI, Sstvala, Sstvecd, Zbb, Zbkc, Zibi, Zk.
RISC-V International
The spec repos saw 30 commits this month, led by ISA Manual with 28 commits.
Spec Repository Activity
Repository
Commits
Contributors
ISA Manual
28
12
Debug Spec
1
1
SBI Spec
1
1
Community Buzz (r/RISCV)
The most popular posts on
r/RISCV this month,
ranked by upvotes.
Linux Kernel (RISC-V) had a solid month with 85 commits from 40 contributors. Deepak Gupta was the most active contributor with 20 commits. New feature work included 33 commits: "riscv: create a Kconfig fragment for shadow stack and landing pad support"; "arch/riscv: add dual vdso creation logic and select vdso based on hw". Platform and DT work accounted for 19 commits. Bug fixes accounted for 12 commits (14%). ISA extension work spanned 10 commits, touching Zk, Zknh.
33 New features & support19 Device tree / platform support12 Bug fixes10 ISA extensions4 Interrupt controllers (AIA/APLIC/PLIC)3 KVM / Virtualisation3 Performance optimisations2 Vector extension (RVV)2 Cleanup & refactoring
A steady month for QEMU (RISC-V) with 32 commits from 13 contributors. Top contributor: Djordje Todorovic with 9 commits. New feature work included 12 commits: "riscv/boston-aia: Add an e1000e NIC in slot 0 func 1"; "hw/riscv: Add support for MIPS Boston-aia board mode". Bug fixes accounted for 4 commits (12%).
12 New features & support4 Compiler backend / code generation4 Bug fixes2 ISA extensions2 Interrupt controllers (AIA/APLIC/PLIC)2 Cleanup & refactoring1 Vector extension (RVV)
Notable Changes
target/riscv: Add Zilsd and Zclsd extension support (4975960510, lxx)
hw/riscv: Add support for MIPS Boston-aia board mode (2264f637da, Djordje Todorovic)
hw/riscv: Add support for RISCV CPS (12eda1a6aa, Djordje Todorovic)
target/riscv/cpu: add riscv_dump_csr() helper (c10187b12d, Daniel Henrique Barboza)
target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val (cfc96df65e, Alistair Francis)
hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes (15406cc593, Frank Chang)
target/riscv: print all available CSRs in riscv_cpu_dump_state() (354c16c69f, Daniel Henrique Barboza)
hw/core/loader: Make load_elf_hdr() return bool, simplify caller (7bfd6c0e09, Markus Armbruster)
target/riscv: Combine mhpmcounter and mhpmcounterh (and 6 more) (4fe8ae0906, Anton Johansson)
target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state() (8e35971a56, Daniel Henrique Barboza)
error: Use error_setg_errno() to improve error messages (b351b49275, Markus Armbruster)
Top Contributors
Author
Commits
Djordje Todorovic
9
Anton Johansson
7
Daniel Henrique Barboza
3
Peter Maydell
2
Richard Henderson
2
Markus Armbruster
2
Philippe Mathieu-Daudé
1
Cédric Le Goater
1
Roan Richmond
1
lxx
1
GCC (RISC-V)
19
Commits
8
Contributors
1192
Lines Added
563
Lines Removed
GCC (RISC-V) saw moderate activity with 19 commits from 8 contributors. Robin Dapp was the most active contributor with 6 commits. Bug fixes accounted for 6 commits (31%).
6 Bug fixes4 New features & support2 ISA extensions2 Compiler backend / code generation1 Vector extension (RVV)1 Cleanup & refactoring1 Performance optimisations
Notable Changes
RISC-V: Add zvfbfmin to tt-ascalon-d8's extension list [PR123492] (and 2 more) (c9058b7671, Peter Bergner)
RISC-V: Add support for _BitInt [PR117581] (808b684172, Kito Cheng)
targethooks: Change SAME_FUNCTION_VERSIONS hook to support checking mergeability (3ecc4d571f, Alfie Richards)
[RISC-V][PR rtl-optimization/121787] Work around bad cfglayout interaction with asm goto (63e0c271e9, Jeff Law)
[PATCH v1 1/2] RISC-V: Fix incorrect combine pattern for any_extend [PR123317] (2dbf9c0fec, Pan Li)
[RISC-V] Restore inline expansion of block moves on RISC-V in some cases (0c3d8dd928, Jeff Law)
Partially revert patch that made VXRM a global register on RISC-V (08ccc67ef4, Jeff Law)
[RISC-V][PR target/123626] Fix VXRM state after calls (6b79f1a5b8, Jeff Law)
[RISC-V] Clamp long reservations to 7c (8265192910, Jeff Law)
doc: make regenerate-opt-urls (c53c1ce78e, Sandra Loosemore)
Update copyright years. (254a858ae7, Jakub Jelinek)
Top Contributors
Author
Commits
Robin Dapp
6
Jeff Law
5
Peter Bergner
3
Sandra Loosemore
1
Kito Cheng
1
Alfie Richards
1
Pan Li
1
Jakub Jelinek
1
LLVM (RISC-V)
189
Commits
42
Contributors
140678
Lines Added
28438
Lines Removed
Plenty of action in LLVM (RISC-V) this month: 189 commits from 42 contributors. +140,678/-28,438 lines changed — a big diff. Leading the charge was Craig Topper with 61 commits. New feature work included 76 commits: "[DAG] Reland: Enable bitcast STLF for Constant/Undef (#178890)"; "Revert "[DAG] Enable bitcast STLF for Constant/Undef" (#178872)". ISA extension work spanned 46 commits, touching QC_EXTU, QC_E_ADDAI, Zbb, Zbkc, Zibi, Zvbc. Backend and code generation work was the biggest theme at 43 commits.
76 New features & support58 Cleanup & refactoring46 ISA extensions43 Compiler backend / code generation15 Vector extension (RVV)14 Bug fixes4 Performance optimisations
Notable Changes
[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (#174920) (6902f3310e, Boyao Wang)
[RISCV] Add ZZZ_ to some inline assembly vector register classes to sort them after VR/VRNoV0 in regclass enum. (#177087) (73a309e20e, Craig Topper)
[LV] Add support for llvm.vector.partial.reduce.fadd (#163975) (762ba885f9, Damian Heaton)
[RISCV] Use static arrays+ArrayRef instead of SmallVector to select P extension vector VTs. NFC (#175390) (00915b22ff, Craig Topper)
[RISCV] Add support for XAndesPerf branch on immediate in RISCVRedundantCopyElimination (#174706) (5185f07a37, Jim Lin)
[RISCV] Add missing HasStdExtZvkb Predicate to some of the vector rotate patterns. NFC (#178250) (72c9304bb9, Craig Topper)
[RISCV] Add support for Xqcibi branch on immediate in RISCVRedundantCopyElimination (#174358) (41c5830aab, Sudharsan Veeravalli)
[RISCV] Add a template function for disassembling LMUL=2/4/8 vector registers. NFC (#177681) (97c4a5fc1d, Craig Topper)
[RISCV] Add the missing SEW search table field to vector FMA instructions (#175646) (ed9f5c93dc, Min-Yih Hsu)
[RISCV] Add SimplifyDemandedBits and hasAllNBitUsers support for CLSW. (#174542) (551d55397a, Craig Topper)
[SelectionDAG] Add very basic computeKnownBits support for ISD::CLMUL. (#177445) (53b0a64e98, Craig Topper)
[RISCV][llvm] Handle calling convention for P extension fixed vectors (#176093) (2a8a694b50, Brandon Wu)
[RISCV] Support ISD::CLMUL/CLMULH for i64 scalable vectors with Zvbc. (#178340) (80cbd1d696, Craig Topper)
[RISCV] Add isCommutable=1 to some binary P extension instructions. (#175692) (a0e0775d91, Craig Topper)
Top Contributors
Author
Commits
Craig Topper
61
Brandon Wu
24
Sudharsan Veeravalli
12
Sam Elliott
8
Jim Lin
8
Francesco Petrogalli
7
Mikhail Gudim
7
Luke Lau
5
Pengcheng Wang
5
Alexander Richardson
5
glibc (RISC-V)
3
Commits
2
Contributors
135
Lines Added
132
Lines Removed
Minimal activity in glibc (RISC-V): 3 commits from 2 contributors. Yao Zihong was the driving force, authoring 2 of 3 commits (66%). Cleanup and refactoring made up 1 commit (33%).
1 Cleanup & refactoring
Notable Changes
riscv: Disable multiarch memcpy variants when !IS_IN(libc) (343b7918da, Yao Zihong)
riscv: Disable multiarch memset variants when !IS_IN(libc) (39d9fa9e31, Yao Zihong)
Update copyright dates with scripts/update-copyrights (66f3e9219d, Paul Eggert)
GDB (RISC-V) had exactly one commit this month. Cleanup and refactoring made up 1 commit (100%).
1 Cleanup & refactoring
Notable Changes
Update copyright dates to include 2026 (4abc1ce2cc, Tom Tromey)
Top Contributors
Author
Commits
Tom Tromey
1
U-Boot (RISC-V)
4
Commits
3
Contributors
1274
Lines Added
1274
Lines Removed
A light month for U-Boot (RISC-V) with 4 commits from 3 contributors.
1 Cleanup & refactoring1 Device tree / platform support
Notable Changes
riscv: Update linker scripts to ensure appended device tree is aligned (f150843499, Tom Rini)
board: nxp: Rename board directory from board/freescale to board/nxp (add12cb688, Alice Guo)
Revert "doc: board: starfive: update jh7110 common description" (d503633a36, Tom Rini)
doc: board: starfive: update jh7110 common description (8304f32267, E Shattow)
Top Contributors
Author
Commits
Tom Rini
2
Alice Guo
1
E Shattow
1
OpenOCD (RISC-V)
4
Commits
4
Contributors
10
Lines Added
2
Lines Removed
Minimal activity in OpenOCD (RISC-V): 4 commits from 4 contributors.
3 New features & support1 Bug fixes
Notable Changes
configure.ac: Replace --enable-verbose-usb-comms with a new runtime log level. (ea9afa9e3e, R. Diez)
doc: add STM32WBA as supported by flash driver 'stm32l4x' (b36de4f539, Antonio Borneo)
doc/opencocd.texi: mention support of PIC32CZ CA70 (587c783103, Michal Lenc)
target/riscv: fix riscv exec_progbuf for SMP targets (ad0ed194f5, Samuel Obuch)
Top Contributors
Author
Commits
Antonio Borneo
1
R. Diez
1
Michal Lenc
1
Samuel Obuch
1
Eigen (RISC-V)
2
Commits
1
Contributors
1070
Lines Added
576
Lines Removed
Eigen (RISC-V) was quiet this month with 2 commits. Most of the work came from Chip Kerchner (2 of 2 commits, 100%). The vector extension (RVV) saw 2 commits of continued development.
2 Vector extension (RVV)1 Bug fixes
Notable Changes
Initial version of reactivating RVV features like GeneralBlockPanelKernel (5d9beb81ab, Chip Kerchner)
Fix more packetmath issues for RVV (7aea350ba1, Chip Kerchner)
Top Contributors
Author
Commits
Chip Kerchner
2
Linux Kernel Docs & DT (RISC-V)
9
Commits
3
Contributors
200
Lines Added
14
Lines Removed
Linux Kernel Docs & DT (RISC-V) saw lighter activity with 9 commits from 3 contributors. Guodong Xu dominated with 7/9 commits (77%). Board and device tree support got 9 commits. Work on Sstvala, Sstvecd accounted for 6 commits. New feature work included 6 commits: "dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings"; "dt-bindings: riscv: add SpacemiT X100 CPU compatible".
9 Device tree / platform support6 ISA extensions6 New features & support