Linux Kernel (RISC-V) kept moving with 23 commits from 14 contributors. KVM and virtualisation received 8 patches. New feature work included 6 commits: "Convert 'alloc_flex' family to use the new default GFP_KERNEL argument"; "Convert 'alloc_obj' family to use the new default GFP_KERNEL argument". AIA and interrupt controller work accounted for 4 patches.
8 KVM / Virtualisation6 New features & support4 Interrupt controllers (AIA/APLIC/PLIC)3 Bug fixes2 Security & memory safety fixes2 Vector extension (RVV)2 ISA extensions1 Performance optimisations1 Device tree / platform support
Notable Changes
bpf, riscv: add fsession support for trampolines (35b3515be0, Menglong Dong)
Convert 'alloc_flex' family to use the new default GFP_KERNEL argument (323bbfcf1e, Linus Torvalds)
Convert 'alloc_obj' family to use the new default GFP_KERNEL argument (bf4afc53b7, Linus Torvalds)
bpf, riscv: introduce emit_store_stack_imm64() for trampoline (93fd420d71, Menglong Dong)
riscv: KVM: allow Zilsd and Zclsd extensions for Guest/VM (f326e846ff, Pincheng Wang)
OpenSBI kept moving with 32 commits from 6 contributors. Vladimir Kondratiev dominated with 22/32 commits (68%). New feature work included 9 commits: "platform: generic: eyeq7h: enable ECC on L1 cache"; "platform: generic: mips: add P8700 based "eyeq7h" and "boston"". Bug fixes accounted for 4 commits (12%).
9 New features & support4 Bug fixes
Notable Changes
lib: utils/serial: Add support for Altera JTAG UART (b07e449d15, Icenowy Zheng)
lib: utils/cache: add cache enable function (6d26b43c47, Ben Zong-You Xie)
platform: generic/andes: add CSR save and restore functions for AE350 platform (85bff9cc16, Ben Zong-You Xie)
lib: sbi_pmu: Add FW counter index validation when reading high bits on RV64 (9656943bd3, James Raphael Tiovalen)
platform: generic: eyeq7h: enable ECC on L1 cache (and 19 more) (8d1c21b387, Vladimir Kondratiev)
platform: generic: mips p8700: Add match data for CM info (bc2722b0f3, Benoît Monin)
lib: utils/cache: add Andes last level cache controller (82b0961821, Ben Zong-You Xie)
lib: utils/suspend: add Andes ATCSMU suspend driver (b27ecec76b, Ben Zong-You Xie)
lib: sbi_pmu: Fix multiple FW counter start operations with custom PMU device (a95c36f165, James Raphael Tiovalen)
lib: utils/hsm: factor out ATCSMU code into an HSM driver (9ffacc8ae1, Ben Zong-You Xie)
lib: sbi_hart_pmp: disable unconfigured PMP entries (ea45923765, Vladimir Kondratiev)
firmware: Initialize stack guard via Zkr (ecdb6c90c8, Xiang W)
lib: sbi: print hartid in hex (e58d528702, Vladimir Kondratiev)
QEMU (RISC-V) saw lighter activity with 13 commits from 3 contributors. Philippe Mathieu-Daudé was the driving force, authoring 10 of 13 commits (76%).
1 Cleanup & refactoring
Notable Changes
exec: Drop TARGET_PHYS_ADDR_SPACE_BITS (cf884c075e, Anton Johansson)
hw/nvram/fw_cfg: Rename fw_cfg_init_mem_wide() -> fw_cfg_init_mem_dma() (99d1b03365, Philippe Mathieu-Daudé)
target/riscv: Remove unnecessary target_ulong type uses (and 5 more) (de32a75647, Philippe Mathieu-Daudé)
disas: Have disas_set_info() take a const CPUState (a63b90ca6c, Philippe Mathieu-Daudé)
monitor: Reduce target-specific declarations (a9edda7250, Philippe Mathieu-Daudé)
disas/riscv: Make rv_decode::cfg const (8a00198ab4, Philippe Mathieu-Daudé)
hw/riscv: Set IOMMU PAS via property (3a3cfcb29f, Anton Johansson)
Top Contributors
Author
Commits
Philippe Mathieu-Daudé
10
Anton Johansson
2
Pierrick Bouvier
1
GCC (RISC-V)
14
Commits
4
Contributors
445
Lines Added
46
Lines Removed
GCC (RISC-V) saw lighter activity with 14 commits from 4 contributors. Robin Dapp was the most active contributor with 6 commits. Vector extension support moved forward with 5 commits. Bug fixes accounted for 5 commits (35%).
5 Vector extension (RVV)5 Bug fixes3 ISA extensions3 New features & support1 Compiler backend / code generation1 Performance optimisations
Notable Changes
RISC-V: Add another combine pattern for vfmin/max on cost model (and 2 more) (63fc48f077, Pan Li)
[RISC-V][PR rtl-optimization/123322] Split general conditional moves into simpler sequences (e7c2fd08ce, Jeff Law)
[PR target/123911][RISC-V] Fix infinite recursion in riscv_legitimize_move (2f84ad4ddc, Jeff Law)
RISC-V: Consider uses for vsetvl LCM transparency. [PR122448] (and 5 more) (0635bfb53a, Robin Dapp)
[RISC-V][PR target/124048] Fix RTL generated by conditional AND splitter (3a7143ed83, Jeff Law)
[PR target/124147] Fix build failure with clang on RISC-V (136ef3b4dd, Jeff Law)
[PATCH] RISC-V: fix nullptr dereference in parse_arch (09d7a79c79, Yangyu Chen)
It was a busy month in LLVM (RISC-V) land, with 167 commits from 36 contributors. +110,220/-64,770 lines changed — a big diff. Leading the charge was Craig Topper with 85 commits. Code housekeeping was a significant theme at 53 commits (31%). New feature work included 50 commits: "[RISCV] Add Defs = VXSAT to P extension instructions. (#183455)"; "[RISCV] Add processor definitions for XuanTie C910V2 and C920V2 (#174056)". The compiler backend saw heavy activity with 46 commits touching code generation. Extension support saw 29 commits covering Zba, Zbb, Zbkb, Zicsr, Zmmul, Zvabd.
53 Cleanup & refactoring50 New features & support46 Compiler backend / code generation29 ISA extensions9 Performance optimisations7 Vector extension (RVV)5 Bug fixes
Notable Changes
[RISCV] Add basic scalar support for MERGE, MVM, and MVMN from P extension (#180677) (31e1bcfd09, Craig Topper)
[RISCV][llvm] Support INSERT_VECTOR_ELT codegen for P extension (#179471) (d99f1cdd66, Brandon Wu)
Revert "[LLD] Add support for statically resolved vendor-specific RISCV relocations. (#169273)" (#181336) (78d995758d, Fangrui Song)
[RISC] Rename the P extensions srx/slx tests and add fshl/fshr intrinsic tests. NFC (#180984) (9a496ddca3, Craig Topper)
[RISCV] Partial support for using PPAIRE.B/H to optimize unaligned load sequences. (#183423) (8533889a54, Craig Topper)
[RISCV] Use PADD_DW instead of ADDD for GPRPair copy on RV32 with P extension (#181316) (b39ab2e0ef, Craig Topper)
[RISCV] Introduce a new syntax for processor-specific tuning feature strings (#175063) (6441f1c9d5, Min-Yih Hsu)
Just a single commit landed in GDB (RISC-V) this month. Almost entirely a bug-fix month at 100% (1 of 1 commits).
1 Bug fixes
Notable Changes
[gdb] Fix typo recordered -> recorded (96cc0a530d, Tom de Vries)
Top Contributors
Author
Commits
Tom de Vries
1
Rust (RISC-V)
1
Commits
1
Contributors
2
Lines Added
2
Lines Removed
One lone commit for Rust (RISC-V) this month. This was primarily a stabilisation month — 1 of 1 commits (100%) were fixes.
1 Bug fixes
Notable Changes
Fix typos in riscv64a23-unknown-linux-gnu.md (34cdaebf37, Wolf Vollprecht)
Top Contributors
Author
Commits
Wolf Vollprecht
1
OpenOCD (RISC-V)
4
Commits
3
Contributors
26
Lines Added
3
Lines Removed
Minimal activity in OpenOCD (RISC-V): 4 commits from 3 contributors.
2 New features & support1 ISA extensions
Notable Changes
configure.ac: Replace --enable-malloc-logging with a new runtime log level. (129e9d3005, R. Diez)
README: Use Markdown extension (bcfa2bc6b5, Marc Schink)
flash: ROM support (8ee7cb12cf, Tomas Vanek)
flash: read only alias (2b986178cf, Tomas Vanek)
Top Contributors
Author
Commits
Tomas Vanek
2
R. Diez
1
Marc Schink
1
OpenBLAS (RISC-V)
12
Commits
1
Contributors
2375
Lines Added
485
Lines Removed
A quieter month for OpenBLAS (RISC-V), with 12 commits. Chip Kerchner was the driving force, authoring 12 of 12 commits (100%). Vector extension support moved forward with 1 commit.
4 New features & support1 Vector extension (RVV)1 ISA extensions
Notable Changes
Convert inputs from BF16 to FP32 and use FP32 vector madds. 18% faster. (33560437f5, Chip Kerchner)
Fixed MADD to use float16 values. Use LMUL = 2 in main loop. Now 1.85X faster on BananaPi. (e3cb067bf4, Chip Kerchner)
Add flag for not converting A & B - will be used in future to do conversion during packing. (7a1d23400f, Chip Kerchner)
Added ability to accumulate in FP16 for GEMM. Widens once at the end of loops. (b5f2a50fe9, Chip Kerchner)
Convert BF16 values once (and vectorized). (4121a22c02, Chip Kerchner)
Add dummy memsets - just in case. (1d6aa0dc31, Chip Kerchner)
Add pre-RVA23 to BF16 GEMM. (efe63e7970, Chip Kerchner)
Forget to add defintion. (74d9fe2832, Chip Kerchner)
Only convert B if M is greater or equal to 4. (1cc377ef61, Chip Kerchner)
Conversion from BF16 to FP32 only once. (0acb60aab3, Chip Kerchner)