RISC-V Software News

March 2026 — Upstream Open Source Activity

The Big Picture

March brought 218 commits across 13 projects in the RISC-V stack. LLVM (RISC-V) led with 130 commits (59%). Also active: Linux Kernel (RISC-V) (17), OpenSBI (15), U-Boot (RISC-V) (15). Hardening efforts were visible across the stack, with 16 security-related patches. Software support advanced for QC_C_MULIADD, QC_SHLADD, Smpmpmt, Smstateen, Ssaia, Zalrsc, Zbc, Zbkc. Virtualisation saw 14 KVM-related patches. Most-discussed mailing list thread: "lib: sbi: domain: ensure boot_hartid is assigned (2-patch series)" (OpenSBI, 9 replies).

RISC-V International

RISC-V International is tracking 100 specifications, of which 48 have been ratified. Currently 21 are in the home stretch (freeze/stabilisation/ratification-ready), 8 under active development, and 15 in planning. Specs flagged as "exposed" (at risk of slipping): Confidential VM Extension (CoVE) with I/O. Keep an eye on these. Across RISC-V International, 74 working groups are tracked — 59 actively meeting, 12 running at low activity. New groups being chartered: Performance Events TG, Parameters SIG, Event Trace TG, Logic Analyzer Trace TG, Speculation Barriers TG . The spec repos saw 50 commits this month, led by ISA Manual with 39 commits.

Specification Pipeline (100 total, 48 ratified)

48
Ratified
19
in Freeze
15
in Planning
8
Under Development
5
Cancelled
3
Inception
2
in Ratification-Ready

Ratification-Ready (2)

Freeze (19)

Development (8)

Planning (15)

Inception (3)

Spec Repository Activity

RepositoryCommitsContributors
ISA Manual 39 15
SBI Spec 6 2
Profiles 3 2
Debug Spec 1 1
ELF psABI 1 1

Working Groups (74 total)

59
Active
12
Low Activity
10
Being Chartered

New Groups Being Chartered

  • Performance Events TG — chaired by Beeman Strong (Meta)
  • Parameters SIG — chaired by Derek Hower (Qualcomm)
  • Event Trace TG — chaired by Bruce Ableidinger (MIPS)
  • Logic Analyzer Trace TG — chaired by Sajosh Janarthanam (Tenstorrent)
  • Speculation Barriers TG — chaired by Ved Shanbhogue (Meta)
  • RVM Profile TG — chaired by Ozgur Ozkurt (Quintauris)
  • Automotive SIG — chaired by Thomas Roecker (Infineon)
  • Long Instruction TG — chaired by Stefan Wallentowitz (Individual Member)
  • JITed and Dynamic Languages SIG — chaired by Martin Maas (Google)
  • Vector Digital Signal Processing TG — chaired by Dmitry Utyansky (Synopsys)

Community Buzz (r/RISCV)

The most popular posts on r/RISCV this month, ranked by upvotes.

Linux Kernel (RISC-V)

17
Commits
7
Contributors
128
Lines Added
49
Lines Removed

A steady month for Linux Kernel (RISC-V) with 17 commits from 7 contributors. Leading the charge was Lukas Gerlach with 5 commits. Virtualisation work accounted for 14 patches, continuing to mature RISC-V KVM support. Bug fixes dominated: 13/17 commits (76%). A month focused on getting things right. Security dominated the month (11 commits, 64%). Highlights: "irqchip/riscv-rpmi-sysmsi: Fix mailbox channel leak in rpmi_sysmsi_probe()"; "KVM: riscv: Fix Spectre-v1 in PMU counter access". AIA and interrupt controller work accounted for 6 patches.

14 KVM / Virtualisation 13 Bug fixes 11 Security & memory safety fixes 6 Interrupt controllers (AIA/APLIC/PLIC) 3 ISA extensions 1 New features & support 1 Device tree / platform support

Notable Changes

  • RISC-V: KVM: Check host Ssaia extension when creating AIA irqchip (and 2 more) (c61ec3e8cc, Anup Patel)
  • RISC-V: KVM: Skip THP support check during dirty logging (b342166cbc, Wang Yechao)
  • RISC-V: KVM: Fix potential UAF in kvm_riscv_aia_imsic_has_attr() (and 3 more) (7120a9d9e0, Jiakai Xu)
  • irqchip/riscv-rpmi-sysmsi: Fix mailbox channel leak in rpmi_sysmsi_probe() (76f0930d6e, Felix Gu)
  • irqchip/riscv-aplic: Do not clear ACPI dependencies on probe failure (620b6ded72, Jessica Liu)
  • KVM: riscv: Fix Spectre-v1 in PMU counter access (and 4 more) (2dda6a9e09, Lukas Gerlach)
  • irqchip/riscv-aplic: Register syscore operations only once (b330fbfd34, Jessica Liu)
  • RISC-V: KVM: fix off-by-one array access in SBI PMU (5c1bb07871, Radim Krčmář)

Top Contributors

AuthorCommits
Lukas Gerlach5
Jiakai Xu4
Anup Patel3
Jessica Liu2
Felix Gu1
Wang Yechao1
Radim Krčmář1

Mailing List Activity

OpenSBI

15
Commits
7
Contributors
481
Lines Added
68
Lines Removed

OpenSBI saw moderate activity with 15 commits from 7 contributors. Top contributor: Anup Patel with 8 commits. Interrupt controller infrastructure (AIA/APLIC/PLIC/IMSIC) received 8 patches. Bug fixes accounted for 4 commits (26%).

8 Interrupt controllers (AIA/APLIC/PLIC) 4 Bug fixes 4 New features & support 2 Security & memory safety fixes 1 ISA extensions 1 Cleanup & refactoring 1 Device tree / platform support

Notable Changes

  • lib: utils/irqchip: Add unique_id to plic, aplic, and imsic data (and 2 more) (e82d20122d, Anup Patel)
  • lib: Use proper add opcode on RV32 with Zalrsc (b5348006e9, Marti Alonso)
  • lib: sbi_init: Call hart init and timer init before platform early init (4813a20420, Yu-Chien Peter Lin)
  • lib: sbi_irqchip: Allow registering interrupt handlers (and 4 more) (0ab0c470d5, Anup Patel)
  • lib: sbi: Fix undefined behavior in signed shifts in sbi_hart.c (2727c43f8d, Marcos Oduardo)
  • lib: fdt_helper: Removed unnecessary dt parsing check (4dc1b9f7ba, Victoriano Morales)
  • platform: generic: mips boston: update "compatible" (ef1ee40e7d, Vladimir Kondratiev)
  • lib: sbi: fix sse_event_inject() status setting (6d5b2b9b05, Charlie Jenkins)
  • include: sbi: Fix illegal shift in sbi_domain.h (3baca10015, Marcos Oduardo)

Top Contributors

AuthorCommits
Anup Patel8
Marcos Oduardo2
Yu-Chien Peter Lin1
Charlie Jenkins1
Marti Alonso1
Vladimir Kondratiev1
Victoriano Morales1

Notable Discussions

Mailing List Activity

QEMU (RISC-V)

13
Commits
8
Contributors
75
Lines Added
50
Lines Removed

Not the busiest month for QEMU (RISC-V): 13 commits from 8 contributors. Bug fixes accounted for 5 commits (38%). RVV work continued with 2 commits touching vector-related code. ISA extension work spanned 1 commit, touching Smpmpmt.

5 Bug fixes 2 Vector extension (RVV) 1 Security & memory safety fixes 1 ISA extensions 1 Interrupt controllers (AIA/APLIC/PLIC) 1 New features & support 1 Cleanup & refactoring 1 Device tree / platform support

Notable Changes

  • target/riscv: Support Smpmpmt extension (58cbdc780b, Jay Chang)
  • target/riscv: rvv: Fix missing flags merge in probe_pages for cross-page accesses (5568177738, Max Chou)
  • hw/riscv/riscv-iommu: Free instance_init allocations in instance_finalize (3d39fd35f6, Peter Maydell)
  • target/riscv: Fix null pointer dereference in cpu_set_exception_base (519f0bdf4c, Djordje Todorovic)
  • hw/riscv: Remove deprecated 'riscv, delegate' device-tree property (f2af8f0d5d, Philippe Mathieu-Daudé)
  • hw/riscv: microchip_pfsoc: Don't call qdev_get_machine in soc init (aa12d98d02, Alistair Francis)
  • target/riscv: Fix scountovf CSR behavior in VS-mode and M-mode (38937473da, Jim Shu)
  • gdbstub: Remove @g_pos argument in gdb_register_coprocessor() (aa6a508795, Philippe Mathieu-Daudé)
  • hw/riscv: Mark RISC-V specific peripherals as little-endian (cf430fa1f1, Philippe Mathieu-Daudé)
  • hw/riscv: sifive_e: Don't call qdev_get_machine in soc init (b0c9d8c126, Alistair Francis)
  • target/riscv: rvv: Fix page probe issues in vext_ldff (0e8ad6a846, Max Chou)
  • hw/riscv: Fix integer overflow in cm_base calculation (6802b477e1, Djordje Todorovic)
  • linux-user: make syscall emulation interruptible (9097087147, Florian Hofhammer)

Top Contributors

AuthorCommits
Philippe Mathieu-Daudé3
Max Chou2
Djordje Todorovic2
Alistair Francis2
Jim Shu1
Jay Chang1
Peter Maydell1
Florian Hofhammer1

GCC (RISC-V)

6
Commits
5
Contributors
49
Lines Added
13
Lines Removed

GCC (RISC-V) saw lighter activity with 6 commits from 5 contributors. The vector extension (RVV) saw 1 commit of continued development.

2 Bug fixes 1 Vector extension (RVV) 1 Compiler backend / code generation 1 Cleanup & refactoring

Notable Changes

  • RISC-V: Allow all vector modes during builtin registration. [PR124613] (79ef3558c8, Robin Dapp)
  • [PATCH] RISC-V: Fix TARGET_CHECK_TARGET_CLONE_VERSION implementation (5a0016576f, Yangyu Chen)
  • fmv: Check DECL_VIRTUAL_P for virtual functions for LTO handling (4ca1de5662, Yangyu Chen)
  • [RISC-V][PR target/124674] Define OImode in the usual way (33e4afffc8, Jeff Law)
  • riscv: Fix formating of diagnostic [PR124403] (8ee479c278, Andrew Pinski)
  • Update copyright years. (e797ddb062, Jakub Jelinek)

Top Contributors

AuthorCommits
Yangyu Chen2
Jeff Law1
Robin Dapp1
Jakub Jelinek1
Andrew Pinski1

LLVM (RISC-V)

130
Commits
45
Contributors
139842
Lines Added
71485
Lines Removed

LLVM (RISC-V) saw heavy activity with 130 commits from 45 contributors. That's +139,842/-71,485 lines of churn. Leading the charge was Craig Topper with 37 commits. Backend and code generation work was the biggest theme at 43 commits. New feature work included 30 commits: "[RISCV] Avoid creating unnecessary node. Add missing break to switch. NFC (#189511)"; "Enable generic overlapping optimization for memmove (#177885)". Work on QC_C_MULIADD, QC_SHLADD, Zbc, Zbkc, Zdinx, Zibi accounted for 21 commits.

43 Compiler backend / code generation 30 New features & support 21 ISA extensions 21 Cleanup & refactoring 15 Vector extension (RVV) 11 Bug fixes 10 Performance optimisations

Notable Changes

  • [DAGCombine] Enable div by constant optimization for odd sized vectors before type legalization. (#188313) (0ebef5e5e2, Craig Topper)
  • [LegalizeVectorOps][RISCV][PowerPC][AArch64][X86] Enable the clmul/clmulr/clmulh expansion code. (#184257) (d20395cfa3, Craig Topper)
  • [RISCV][MC] Add support of Zvzip extension (#185614) (db7e0daa85, Pengcheng Wang)
  • [RISCV] Add register group overlap checks to the assembler for vector indexed segment load (#184963) (763de90db4, joshua-arch1)
  • [RISCV] Add register overlap checks to the assembler for vector indexed segment load (#184569) (f7ca74f600, joshua-arch1)
  • [RISCV] Add codegen patterns to support short forward branches with immediates (#185643) (696208b72c, quic_hchandel)
  • [RISCV][TTI] Implement cost of llvm.experimental.vector.extract.last.active (#184067) (5b60283506, Elvis Wang)
  • [RISCV][P-ext] Support vector ISD::ABS using PABD instructions. (#184822) (bb1d53bbd8, Craig Topper)
  • [RISCV] Add more extensions to spacemit-x100 (#186351) (c389129bcf, Mark Zhuang)
  • [RISCV] Add findCommutedOpIndices support for Zvabd (bbe4853a7b, Pengcheng Wang)
  • [TargetLowering][RISCV] Using index type for step vector in expandVectorFindLastActive (#187984) (494b98236f, Elvis Wang)
  • [RISCV] Add compress pattern for QC_SHLADD Rd, Rs1, Rd, 4 to QC_C_MULIADD Rd, Rs1, 16 (#188516) (655618305e, Sudharsan Veeravalli)
  • [RISCV] Refactor lowerBUILD_VECTOR splat opcode selection to avoid duplication. NFC. (#185573) (2410418d06, Jim Lin)
  • [SelectionDAG] Optimize 32-bit udiv with 33-bit magic constants on 64-bit targets (#181288) (3e24a39357, MITSUNARI Shigeo)
  • [RISCV][P-ext] Recognize vector shifts with splat build_vector shift amount. (#184909) (b51859cb3d, Craig Topper)

Top Contributors

AuthorCommits
Craig Topper37
Jim Lin14
Luke Lau11
Pengcheng Wang6
Sam Elliott4
Min-Yih Hsu4
Alexis Engelke4
Kito Cheng3
joshua-arch13
Mark Zhuang2

glibc (RISC-V)

2
Commits
2
Contributors
24
Lines Added
4
Lines Removed

A light month for glibc (RISC-V) with 2 commits from 2 contributors. Vector extension support moved forward with 1 commit.

1 Vector extension (RVV)

Notable Changes

  • riscv: Resolve calls to memcpy using memcpy-generic in early startup (89edb2e8c6, Adhemerval Zanella Netto)
  • riscv: Treat clang separately in RVV compiler checks (a604d62daa, Zihong Yao)

Top Contributors

AuthorCommits
Adhemerval Zanella Netto1
Zihong Yao1

Binutils (RISC-V)

4
Commits
1
Contributors
44
Lines Added
42
Lines Removed

Minimal activity in Binutils (RISC-V): 4 commits. Most of the work came from Alan Modra (4 of 4 commits, 100%).

2 Security & memory safety fixes 1 New features & support

Notable Changes

  • buffer overflow in loongarch_elf_add_sub_reloc_uleb128 (453fdb2d1f, Alan Modra)
  • gas: only free on exit when --enable-leak-check (eced22e468, Alan Modra)
  • gas: don't duplicate include of config.h (ca00826680, Alan Modra)
  • Remove bfd_boolean from gas and gprofng (cc912720b0, Alan Modra)

Top Contributors

AuthorCommits
Alan Modra4

GDB (RISC-V)

10
Commits
3
Contributors
69
Lines Added
62
Lines Removed

A quieter month for GDB (RISC-V), with 10 commits from 3 contributors. Simon Marchi dominated with 8/10 commits (80%).

1 Bug fixes

Notable Changes

  • gdb, gdbserver, gdbsupport: replace many uses of strcmp with streq (b73d92e2c5, Simon Marchi)
  • gdb: change gdbarch_print_registers_info parameter to bool (and 5 more) (5452abae84, Simon Marchi)
  • gdb/riscv: use register number for 'info reg' output format choice (e5425f2687, Andrew Burgess)
  • gdb/gdbtypes: replace TYPE_SAFE_NAME macro with method (7662807a0b, Simon Marchi)
  • [gdb/record] Fix syscall exit recording for riscv (a570ac19e3, Tom de Vries)

Top Contributors

AuthorCommits
Simon Marchi8
Tom de Vries1
Andrew Burgess1

U-Boot (RISC-V)

15
Commits
7
Contributors
121
Lines Added
1052
Lines Removed

U-Boot (RISC-V) saw moderate activity with 15 commits from 7 contributors. A net deletion month (+121/-1,052) — always satisfying. Hal Feng was the most active contributor with 5 commits. New feature work included 6 commits: "riscv: Add support for BeagleV-Fire"; "doc: board: starfive: Add Xunlong OrangePi RV".

6 New features & support 1 Bug fixes 1 Device tree / platform support

Notable Changes

  • riscv: Add support for BeagleV-Fire (b51e59c8b3, Jamie Gibbons)
  • board: starfive: visionfive2: Add Orange Pi RV selection by product_id (b2c92a7b1f, E Shattow)
  • board: starfive: visionfive2: Add VisionFive 2 Lite fdt selection (52c382798c, Hal Feng)
  • eeprom: starfive: Support eeprom data format v3 (and 2 more) (ab4f610deb, Hal Feng)
  • board: starfive: spl: Support VisionFive 2 Lite (f566788ca1, Hal Feng)
  • doc: board: starfive: jh7110 common update OPENSBI build env reference (and 2 more) (1edeb52086, E Shattow)
  • riscv: mpfs: SIFIVE_CLINT and SPL_SIFIVE_CLINT don't exist (12a9c83cba, Heinrich Schuchardt)
  • riscv: don't imply non-existent CONFIG_IP_DYN (7d5c2834c7, Heinrich Schuchardt)
  • driver: cache: Remove SiFive PL2 driver (61e2430360, Nick Hu)
  • sifive: switch to OF_UPSTREAM (4dcff3b572, Andreas Schwab)
  • riscv: Call bootm_final() (aa5ada5447, Simon Glass)

Top Contributors

AuthorCommits
Hal Feng5
E Shattow4
Heinrich Schuchardt2
Simon Glass1
Jamie Gibbons1
Nick Hu1
Andreas Schwab1

Rust (RISC-V)

2
Commits
1
Contributors
107
Lines Added
88
Lines Removed

A light month for Rust (RISC-V) with 2 commits. Most of the work came from Ralf Jung (2 of 2 commits, 100%). Refactoring work accounted for 1 commit (50%).

1 Cleanup & refactoring

Notable Changes

  • target specs: rename abi to cfg_abi (40ebcc031d, Ralf Jung)
  • enum-ify llvm_abiname (6b1487698c, Ralf Jung)

Top Contributors

AuthorCommits
Ralf Jung2

OpenOCD (RISC-V)

1
Commits
1
Contributors
6
Lines Added
1
Lines Removed

Just a single commit landed in OpenOCD (RISC-V) this month.

Notable Changes

  • server: Make "exit" command behave consistently (0c6fe74351, Jan Matyas)

Top Contributors

AuthorCommits
Jan Matyas1

musl libc (RISC-V)

2
Commits
2
Contributors
26
Lines Added
0
Lines Removed

A light month for musl libc (RISC-V) with 2 commits from 2 contributors.

Notable Changes

  • riscv: don't define fenv macros for soft float (1969500402, Alex Rønne Petersen)
  • update syscalls up to linux 6.19 (5c901bb360, Szabolcs Nagy)

Top Contributors

AuthorCommits
Alex Rønne Petersen1
Szabolcs Nagy1

OpenBLAS (RISC-V)

1
Commits
1
Contributors
13
Lines Added
11
Lines Removed

Just a single commit landed in OpenBLAS (RISC-V) this month. Optimisation efforts accounted for 1 commit.

1 Performance optimisations

Notable Changes

  • Optimize ZROT_RVV for the non-unit-stride case (aa967ef6ba, daichengrong)

Top Contributors

AuthorCommits
daichengrong1