RISC-V Software News

April 2026 — Upstream Open Source Activity

The Big Picture

A lighter April with 94 commits across 7 projects. QEMU (RISC-V) led with 50 commits (53%). Also active: GCC (RISC-V) (26), OpenSBI (7), OpenBLAS (RISC-V) (5). Extension support work touched Zbkb. Most-discussed mailing list thread: "RISC-V: Allow RVV reg overlap of v[sz]ext.vf2 for m2" (GCC (RISC-V), 12 replies).

RISC-V International

RISC-V International is tracking 100 specifications, of which 48 have been ratified. Currently 21 are in the home stretch (freeze/stabilisation/ratification-ready), 9 under active development, and 14 in planning. Specs flagged as "exposed" (at risk of slipping): Confidential VM Extension (CoVE) with I/O. Keep an eye on these. Across RISC-V International, 73 working groups are tracked — 57 actively meeting, 8 running at low activity. New groups being chartered: Performance Events TG, Parameters SIG, Event Trace TG, Logic Analyzer Trace TG, Speculation Barriers TG . The spec repos saw 4 commits this month, led by ELF psABI with 3 commits.

Spec Pipeline Changes (since March 2026)

  • RISC-V Quality of Service Controllers Table (RQSC) — Freeze → Ratification-Ready
  • RHTI trcstate Extension — Planning → Development

New specs entering the pipeline:

  • Branch with Immediate (Zibi) (Freeze)
  • Dot-Product (Zvqdot/Zvdot4a8i) (Development)

Specs removed from pipeline:

  • Server Platform (was: Ratification-Ready)
  • Integrated Matrix Extension (IME) (was: Development)

Specification Pipeline (100 total, 48 ratified)

48
Ratified
19
in Freeze
14
in Planning
9
Under Development
5
Cancelled
3
Inception
2
in Ratification-Ready

Ratification-Ready (2)

Freeze (19)

Development (9)

Planning (14)

Inception (3)

Spec Repository Activity

RepositoryCommitsContributors
ELF psABI 3 3
Profiles 1 1

Working Groups (73 total)

57
Active
8
Low Activity
10
Being Chartered

New Groups Being Chartered

  • Performance Events TG — chaired by Beeman Strong (Meta)
  • Parameters SIG — chaired by Derek Hower (Qualcomm)
  • Event Trace TG — chaired by Bruce Ableidinger (MIPS)
  • Logic Analyzer Trace TG — chaired by Sajosh Janarthanam (Tenstorrent)
  • Speculation Barriers TG — chaired by Ved Shanbhogue (Meta)
  • RVM Profile TG — chaired by Ozgur Ozkurt (Quintauris)
  • Automotive SIG — chaired by Thomas Roecker (Infineon)
  • Long Instruction TG — chaired by Stefan Wallentowitz (Individual Member)
  • JITed and Dynamic Languages SIG — chaired by Martin Maas (Google)
  • Vector Digital Signal Processing TG — chaired by Dmitry Utyansky (Synopsys)

OpenSBI

7
Commits
3
Contributors
667
Lines Added
6
Lines Removed

Not the busiest month for OpenSBI: 7 commits from 3 contributors. Leading the charge was Yu-Chien Peter Lin with 4 commits. The interrupt subsystem got 1 patch of attention this month.

5 New features & support 1 ISA extensions 1 Interrupt controllers (AIA/APLIC/PLIC) 1 Bug fixes

Notable Changes

  • platform: sifive: Add initial support for SiFive development platform (0402b8e3dc, Yu-Chien Peter Lin)
  • sifive_dev_platform: Set default MMIO region when SmePMP is enabled (9e14e03032, Yu-Chien Peter Lin)
  • lib: utils: Add MPXY client driver for RPMI MM service group (0b041e58c0, Ranbir Singh)
  • lib: sbi_bitmap_test: add tests for bitmap_empty() (2257e99571, Yu-Chien Peter Lin)
  • include: sbi_bitmap: add bitmap_empty() function (ff7d245b86, Yu-Chien Peter Lin)
  • lib: tests: Add test for string (fdb78b0ec5, Chen Pei)
  • lib: Fix sbi_strchr to correctly handle null terminator search (2bf0de88c8, Chen Pei)

Top Contributors

AuthorCommits
Yu-Chien Peter Lin4
Chen Pei2
Ranbir Singh1

Notable Discussions

Mailing List Activity

QEMU (RISC-V)

50
Commits
17
Contributors
1758
Lines Added
649
Lines Removed

A productive month for QEMU (RISC-V) with 50 commits from 17 contributors. Top contributor: Philippe Mathieu-Daudé with 12 commits. New feature work included 12 commits: "target/riscv: Add a helper to return the current effective priv mode"; "target/riscv: tt-ascalon: Add Tenstorrent mvendorid". Bug fixes accounted for 7 commits (14%). RVV work continued with 5 commits touching vector-related code.

12 New features & support 9 ISA extensions 7 Bug fixes 5 Vector extension (RVV) 1 KVM / Virtualisation 1 Cleanup & refactoring 1 Device tree / platform support

Notable Changes

  • target/riscv: rvv: Support Zvfbfa vector bf16 operations (and 2 more) (ec751ce6a6, Max Chou)
  • hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support (0f035e9830, Jay Chang)
  • target/riscv: rvv: Handle mask/source overlap of vector reduction instructions (4d82676cfc, Anton Blanchard)
  • tcg/translator: add parameter to translator_loop for current addr type (2578f3b68b, Pierrick Bouvier)
  • target/riscv: Expose Zvfbfa extension as a cpu property (and 5 more) (214307f523, Max Chou)
  • hw/riscv/virt-acpi-build.c: Use kvm timer frequency when kvm enabled (4cb2f91773, Yicong Yang)
  • target/riscv: rvv: Allow fractional LMUL on vector SHA instructions (26f6d70954, Anton Blanchard)
  • target/riscv: tt-ascalon: Add Tenstorrent mvendorid (dc634aa347, Joel Stanley)
  • target/riscv: add draft RISC-V Zbr ext as xbr0p93 (32bbab666e, Emmanuel Blot)
  • target/riscv: fix address masking (fb9d616819, Yong-Xuan Wang)
  • target/riscv: Fix pointer masking translation mode check bug (and 6 more) (fabf2446e7, Frank Chang)
  • hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug (841613d240, Jay Chang)
  • hw/riscv/boot: Warn if a ELF format file is loaded as a binary (971851b046, Nicholas Piggin)
  • target/riscv: Use ELEN for Fractional LMUL check (and 2 more) (5dcc64828d, Alistair Francis)
  • target/riscv: fix stale ptshift and base on page walk restart (b2e874bfec, Sebastián Alba Vives)

Top Contributors

AuthorCommits
Philippe Mathieu-Daudé12
Max Chou9
Frank Chang7
Alistair Francis3
Jay Chang3
Anton Blanchard2
Bruno Sa2
Frédéric Pétrot2
Emmanuel Blot2
Yong-Xuan Wang1

GCC (RISC-V)

26
Commits
14
Contributors
739
Lines Added
129
Lines Removed

A steady month for GCC (RISC-V) with 26 commits from 14 contributors. Leading the charge was Jeff Law with 9 commits. 5 commits targeted performance improvements. RVV work continued with 4 commits touching vector-related code. Work on Zbkb accounted for 3 commits. The thread "RISC-V: Allow RVV reg overlap of v[sz]ext.vf2 for m2" generated notable discussion with 12 replies.

5 New features & support 5 Performance optimisations 4 Vector extension (RVV) 3 ISA extensions 2 Compiler backend / code generation 2 Bug fixes

Notable Changes

  • [PATCH 2/3] RISC-V: Enable address tagging on 64-bit targets supporting pointer masking. (e712b42c5e, Maximilian Ciric)
  • [PATCH] RISC-V: Add vector cost model for Spacemit-X60 (2256ae77d4, Milan Tripkovic)
  • vect: replace vect_scalar_cost_multiplier with param_vect_allow_possibly_not_worthwhile_vectorizations (4236a2df4f, Tamar Christina)
  • [PATCH] RISC-V: Support Zalasr extension. (d58044c97e, Jiawei)
  • [RISC-V][PR target/124984] Fix RTL checking abort in thead memory address classification (1917b5a41d, Jeff Law)
  • [V3][RISC-V][PR target/124760] Promote SI to DI in some cases to encourage shNadd insns (6495ab9140, Jeff Law)
  • [RISC-V][PR target/121268] Add splitters to improve andn generation (426bbb72a2, Jeff Law)
  • RISC-V: Add SUBREG_PROMOTED annotation to min/max si3 expansion (58b07289a3, Philipp Tomsich)
  • bitintlower: Padding bit fixes, part 1 [PR123635] (376de66c5a, Jakub Jelinek)
  • [RISC-V][PR rtl-optimization/56096] Improve equality comparisons of a logical AND expressions (5de59c6d82, Jeff Law)
  • [RISC-V][PR tree-optimization/94892] Improve equality test of sign bit splat against zero (1e4294de8e, Jeff Law)
  • [RISC-V][PR target/123838] Improve code generated for shifts with counts 31-N or 63-N (36f0b74a83, Jeff Law)
  • [RISC-V][PR rtl-optimization/80770] Canonicalize extending byte loads for RISC-V (86964edc99, Jeff Law)
  • [4/6] fold-mem-offsets: Move RISC-V size-optimization workaround to the backend (03fcac336e, Philipp Tomsich)
  • [RISC-V][V2][PR target/123839] Improve subset of constant permutes for RISC-V (b9facf8263, Raphael Zinsly)

Top Contributors

AuthorCommits
Jeff Law9
Pan Li2
Philipp Tomsich2
Bohan Lei2
Christoph Müllner2
Jiawei1
Maximilian Ciric1
Monk Chiang1
Milan Tripkovic1
Raphael Zinsly1

Notable Discussions

GDB (RISC-V)

1
Commits
1
Contributors
0
Lines Added
1
Lines Removed

GDB (RISC-V) had exactly one commit this month.

Notable Changes

  • [gdb] Remove unnecessary defs.h/common-defs.h includes (eb221802ed, Tom de Vries)

Top Contributors

AuthorCommits
Tom de Vries1

U-Boot (RISC-V)

1
Commits
1
Contributors
3
Lines Added
3
Lines Removed

One lone commit for U-Boot (RISC-V) this month.

Notable Changes

  • global: Audit Kconfig usage of PARTITION_TYPE_GUID (b0eaaa067e, Tom Rini)

Top Contributors

AuthorCommits
Tom Rini1

OpenOCD (RISC-V)

4
Commits
3
Contributors
74
Lines Added
36
Lines Removed

Minimal activity in OpenOCD (RISC-V): 4 commits from 3 contributors.

1 Bug fixes 1 New features & support

Notable Changes

  • target/riscv: add target_was_examined() checks (7e508338ed, Tomas Vanek)
  • target/riscv: do not set DTM_DTMCS_VERSION_UNKNOWN on examine fail (cc32b36c8f, Tomas Vanek)
  • Fix build issue on MSYS2 and Cygwin (232cd0b0f1, Marc Schink)
  • doc: Update EFM32 documentation (14f652f1bd, Jérôme Pouiller)

Top Contributors

AuthorCommits
Tomas Vanek2
Jérôme Pouiller1
Marc Schink1

OpenBLAS (RISC-V)

5
Commits
1
Contributors
139
Lines Added
201
Lines Removed

A quieter month for OpenBLAS (RISC-V), with 5 commits. The codebase got leaner: +139/-201. Chip Kerchner dominated with 5/5 commits (100%).

Notable Changes

  • Reduce number of vectors in use from 32 to 24 for last stage of main block - now full LMUL2. (cc1b5794a0, Chip Kerchner)
  • Use LMUL2 for calculations in main block - just break them apart before last stage. (22b7950baa, Chip Kerchner)
  • Forgot files from previous check-in. (0a4d6b2e11, Chip Kerchner)
  • Use LMUL2 loads in main block. (3b1aef12c7, Chip Kerchner)
  • Remove shadow variable. (daa3215fb4, Chip Kerchner)

Top Contributors

AuthorCommits
Chip Kerchner5