RISC-V Software News

RISC-V International

RISC-V International is tracking 100 specifications, of which 51 have been ratified. Currently 24 are in the home stretch (freeze/stabilisation/ratification-ready), and 15 in planning. Across RISC-V International, 73 working groups are tracked — 56 actively meeting, 12 running at low activity. New groups being chartered: Performance Events TG, Parameters SIG, Event Trace TG, Logic Analyzer Trace TG, Speculation Barriers TG . The spec repos saw 38 commits this month, led by ISA Manual with 36 commits.

Spec Pipeline Changes (since May 2026)

2 new specifications ratified this month.

RHTI trcstate Extension — Development → Ratification-Ready
Data Trace of Multiple-Memory Access and Compare and Swap — Planning → Freeze
Standard Support Packet extension to E-trace — Development → Freeze
Dot-Product (Zvqdot/Zvdot4a8i) — Development → Stabilization
Performance Event Sampling — Development → Stabilization

New specs entering the pipeline:

Address-Independent Fault Latency (Svukte) (Freeze)
BF16 & Minimal OFP8 Vector Compute (Zvfbfa, Zvfofp8min) (Freeze)
Extra Vector Carry-Less/Crypto Extensions (Zvbc32e, Zvkgs) (Freeze)
Implicit Return (E-Trace 2.0) (Freeze)
RISC-V Worlds (Smwid, Smlwid, Smlwidlist, Smwiddeleg, Sswid) (Freeze)
Fast Interrupts (CLIC) (Stabilization)
Integrated Matrix Extension (IME) (Stabilization)
Shadow Stacks for M-mode, M+U & SPMP (Stabilization)
Vector Unzip Instruction (Zvzip) (Stabilization)
Attached Matrix Extension (AME) (Planning)
CPU Utilization Counter Extension (Sscpuutil) (Planning)
Composable Custom Extensions (Planning)
Data Trace of Multi-Memory Access & CAS (E-Trace 2.0) (Planning)
Instrumentation Trace (Planning)
Performance Events Specification (Planning)
Byte & Halfword LR/SC (Zabhlrsc) (Inception)
Logic Analyzer Trace (Inception)

Specs removed from pipeline:

RISC-V Quality of Service Controllers Table (RQSC) (was: Ratification-Ready)
Additional BF16 and Minimal OFP8 Vector Compute Support (Zvfbfa and Zvfofp8min) (was: Freeze)
Address-Independent Latency of User-Mode Faults to Supervisor Addresses (was: Freeze)
Confidential VM Extension (CoVE) with I/O (was: Freeze)
External Debug Security (was: Freeze)
Extra Vector Carry-Less/Crypto Extensions (was: Freeze)
Input/Output Physical Memory Protection (IOPMP) (was: Freeze)
RISC-V Worlds (was: Freeze)
Security Model (was: Freeze)
Supervisor Domains Access Protection (Smmtt) (was: Freeze)
Implicit Return Extension to the Enhanced Trace for RISC-V 2.0 (was: Development)
Dynamic RVTSO (was: Development)
High Assurance Cryptography (HAC) (was: Development)
Packed Single Instruction Multiple Data - SIMD (P) (was: Development)
Platform Management Interface - RPMI (2.0) (was: Development)
Post-Quantum Cryptography (Keccak) (was: Development)
Sdtrig Enhancements (Sdtrigpend and Sdtrigepm) (was: Development)
Data Trace of Multi-memory Access and Compare & Swap Extension to Enhanced Trace for RISC-V 2.0 (was: Planning)
Zabhlrsc (was: Inception)

Specification Pipeline (100 total, 51 ratified)

51

Ratified

15

in Planning

15

in Freeze

6

Under Stabilization

5

Inception

5

Cancelled

3

in Ratification-Ready

Spec Repository Activity

Repository	Commits	Contributors
ISA Manual	36	15
ELF psABI	2	2

Working Groups (73 total)

56

Active

12

Low Activity

10

Being Chartered

New Groups Being Chartered

Performance Events TG — chaired by Beeman Strong (Meta)
Parameters SIG
Event Trace TG — chaired by Bruce Ableidinger (MIPS)
Logic Analyzer Trace TG — chaired by Sajosh Janarthanam (Tenstorrent)
Speculation Barriers TG — chaired by Ved Shanbhogue (Meta)
RVM Profile TG — chaired by Ozgur Ozkurt (Quintauris)
Automotive SIG — chaired by Thomas Roecker (Infineon)
Long Instruction TG — chaired by Stefan Wallentowitz (Individual Member)
JITed and Dynamic Languages SIG — chaired by Martin Maas (Google)
Vector Digital Signal Processing TG — chaired by Dmitry Utyansky (Synopsys)

OpenSBI

43

Commits

15

Contributors

2920

Lines Added

916

Lines Removed

A productive month for OpenSBI with 43 commits from 15 contributors. Top contributor: Bo Gan with 13 commits. New feature work included 16 commits: "lib: sbi: Add variable-length unprivilege access functions"; "include: sbi: Add GET_RDS_NUM/SET(_FP32/_FP64)_RDS macros". Bug fixes accounted for 7 commits (16%). Interrupt controller infrastructure (AIA/APLIC/PLIC/IMSIC) received 3 patches. Performance work included 3 commits.

16 New features & support 7 Bug fixes 3 Interrupt controllers (AIA/APLIC/PLIC) 3 Performance optimisations 2 Vector extension (RVV) 1 ISA extensions

Notable Changes

platform: generic: Optimize extensions_init() to parse ISA extensions once (ecc92e87a9, Anup Patel)
lib: sbi: Rework misaligned vector load/store (and 5 more) (a8be5e9478, Bo Gan)
lib: sbi: add UBSan support (7bdcf55705, Marcos Oduardo)
include: mailbox: Update RPMI notification structs and add performance events (59fe435b28, David E. Garcia Porras)
include: mailbox: rpmi_msgprot: Add RPMI performance domain flag defines (243035c565, David E. Garcia Porras)
platform: generic: eswin: Add eic770x_hsm and fix warm reset issues (7bff4e529e, Bo Gan)
lib: sbi_mpxy: Enable MPXY channel MSI availability determination (d0ae6a91ff, David E. Garcia Porras)
platform: generic: spacemit: k1: fix wrong address definitions (cc9b4ef8f3, Junhui Liu)
include: utils/hsm: Add __noreturn attribute for sifive_cease (0f42eff6ea, Bo Gan)
include: sbi: Add SBI MPXY notification related defines (b6e7c84ae2, David E. Garcia Porras)
lib: utils/reset: Add litex SoC reset driver (dec9141a77, Inochi Amaoto)
lib: sbi: Drop fw_rw_offset alignment requirement for single fw region (and 7 more) (9c9767504d, Nicholas Piggin)
lib: sbi: Apply budget restriction when polling Zkr CSR state transition (b508e6e25e, Evgeny Voevodin)
lib: sbi_pmu: Honor CLEAR_VALUE/AUTO_START for all hardware event types (3d29f380a6, David E. Garcia Porras)
platform: Fix payload alignment when FW_TEXT_START isn't 2M/4M aligned (895201cc5a, Anirudh Srinivasan)

Top Contributors

Author	Commits
Bo Gan	13
Nicholas Piggin	8
David E. Garcia Porras	6
Anup Patel	4
Michael Ellerman	2
Zong Li	1
liutong	1
Junhui Liu	1
Vladimir Kondratiev	1
Oriol Catalan	1

Notable Discussions

lib: utils: irqchip: implement APLIC hwirq operation hooks 4 replies — Raymond Mao
[PATCH] include: sbi_platform: Increase default stack size 3 replies — Anirudh Srinivasan

Mailing List Activity

Fixes for load/store misaligned and access faults 2 — Bo Gan
Fixes for vector misaligned load/store handlers 2 — Bo Gan
[PATCH] gitignore: Ignore python cache directories 1 — Michael Ellerman
[PATCH v2] lib: sbi: Allow platforms to override local TLB operations 1 — Samuel Holland
include: utils/hsm: Add __noreturn attribute for sifive_cease 1 — Bo Gan
platform: generic: eswin: Add eic770x_hsm and fix warm reset issues — Min Lin
lib: sbi: Do not override emulator callback for vector load/store (4-patch series) — Anup Patel
lib: sbi_mpxy: Enable MPXY channel MSI availability determination — Anup Patel

QEMU (RISC-V)

84

Commits

15

Contributors

2875

Lines Added

1306

Lines Removed

QEMU (RISC-V) had a solid month with 84 commits from 15 contributors. Leading the charge was Anton Johansson with 27 commits. Bug fixes accounted for 24 commits (28%). New feature work included 21 commits: "hw/riscv: add create_fdt_socket_cpu_sifive()"; "hw/riscv: add create_fdt_socket_cpus()".

24 Bug fixes 21 New features & support 4 Device tree / platform support 3 ISA extensions 2 Vector extension (RVV) 1 Security & memory safety fixes 1 Interrupt controllers (AIA/APLIC/PLIC) 1 Cleanup & refactoring

Notable Changes

target/riscv: Add standard B extension implied rule (7e55cb1581, Frank Chang)
target/riscv: Add the implied rule for G extension (65dbf4bfd2, Jim Shu)
hw/watchdog: add k230 watchdog initial support (dace398674, Chao Liu)
hw/riscv: add k230 board initial support (6cf0d08c39, Chao Liu)
target/riscv: add thead-c908 cpu support (2044a97253, Chao Liu)
target/riscv: rvv: Set mstatus.FS dirty when vector FP raises exceptions (66e4d3517b, Max Chou)
hw/riscv/sifive_u.c: add cpu-map, cluster and core DTs (and 2 more) (aedd831f41, Daniel Henrique Barboza)
hw/riscv/boot: Rewrite setup_rom_reset_vec() using load/store API (3df0eb7feb, Philippe Mathieu-Daudé)
target/riscv: Remove target_ulong use in get_physical_address() (8968f8ac7e, Philippe Mathieu-Daudé)
target/riscv/cpu_helper.c: add PMA access fault (and 2 more) (8e090ecfa9, Daniel Henrique Barboza)
target/riscv: De-indent some code in get_physical_address() (64d3884bbf, Philippe Mathieu-Daudé)
hw/riscv: add create_fdt_socket_cpu_sifive() (and 5 more) (e968e487ac, Daniel Henrique Barboza)
target/riscv: Improve PMP address alignment readability (ac02839c2f, Jay Chang)
disas/riscv.c: add 'cbo' insns to disassembler (9273cda722, Daniel Henrique Barboza)
hw/riscv/spike.c: add intc_phandles array (b6cdd8f13e, Daniel Henrique Barboza)

Top Contributors

Author	Commits
Anton Johansson	27
Daniel Henrique Barboza	24
Philippe Mathieu-Daudé	7
Djordje Todorovic	5
Jay Chang	4
Chao Liu	3
Max Chou	2
Frank Chang	2
Anton Blanchard	2
Zephyr Li	2

Mailing List Activity

Re: [PATCH 1/2] hw/riscv/riscv-iommu.c: check for reserved PTE bits — Chao Liu
Re: [PATCH 2/2] hw/riscv/riscv-iommu.c: fault when !PTE_U and no priv access — Chao Liu
Re: [PATCH 2/2] hw/riscv/riscv-iommu.c: fault when !PTE_U and no priv access — Nutty.Liu
Re: [PATCH 1/2] hw/riscv/riscv-iommu.c: check for reserved PTE bits — Nutty.Liu
Re: [PATCH] hw/riscv/riscv-iommu-sys.c: record fault on IOMMU-generated MSI write — Nutty.Liu
Re: [PATCH] hw/riscv/riscv-iommu.c: check reserved MSI PTE basic bits — Nutty.Liu
Support the true Zicclsm extension (5-patch series) — frank.chang
hw/riscv/boot: Describe discontiguous memory in boot_info (3-patch series) — Joel Stanley

glibc (RISC-V)

9

Commits

4

Contributors

1207

Lines Added

6

Lines Removed

A quieter month for glibc (RISC-V), with 9 commits from 4 contributors. Yao Zihong dominated with 6/9 commits (66%). RVV work continued with 7 commits touching vector-related code. New feature work included 6 commits: "riscv: Add RVV memmove for both multiarch and non-multiarch builds"; "riscv: Add RVV strrchr for both multiarch and non-multiarch builds".

7 Vector extension (RVV) 6 New features & support 1 Bug fixes

Notable Changes

riscv: Add RVV memmove for both multiarch and non-multiarch builds (and 5 more) (60f7247847, Yao Zihong)
Remove the jmp_buf stack pointer demangle on ABIs that do not mangle it (c626d764d7, Adhemerval Zanella)
riscv: Fix RV32 libthread_db THREAD_SELF register layout (a014af39fd, Shengwen Cheng)
riscv: Keep __memcmpeq alias with RVV memcmp (9cf4dd03bd, Zihong Yao)

Top Contributors

Author	Commits
Yao Zihong	6
Shengwen Cheng	1
Adhemerval Zanella	1
Zihong Yao	1

Notable Discussions

riscv: Add RVV memcmp for multiarch and non-multiarch 8 replies — Andreas Schwab
[PATCH] riscv: Add big-endian support to string-fzi.h. 5 replies — Florian Weimer

Binutils (RISC-V)

18

Commits

5

Contributors

1430

Lines Added

912

Lines Removed

Binutils (RISC-V) kept moving with 18 commits from 5 contributors. Jan Beulich was the most active contributor with 9 commits. Extension support saw 6 commits covering Smpmpmt, Zvabd. New feature work included 6 commits: "RISC-V: Add support for Smpmpmt v0.6 extension"; "RISC-V: Support Zvabd extension instructions.". The thread "[PATCH] RISC-V: Fix build with GCC-8" generated notable discussion with 14 replies.

6 ISA extensions 6 New features & support 1 Bug fixes 1 Cleanup & refactoring

Notable Changes

RISC-V: Add support for Smpmpmt v0.6 extension (e56bd09181, Jerry Zhang Jian)
RISC-V: Support Zvabd extension instructions. (and 2 more) (d3b84dac94, Jiawei)
RISC-V: Fix build with clang and gcc prior to gcc11 (and 2 more) (7e5ab72bd1, Mark Zhuang)
Re: RISC-V: riscv_parse_subset_t's isa_spec is only parser input (618fc86830, Alan Modra)
bfd/RISC-V: move _bfd_riscv_elf_merge_private_bfd_data() (3a5657bd3f, Jan Beulich)
RISC-V: drop dead code from subset parsing (and 7 more) (de7a82d533, Jan Beulich)
Drop output bfd param from many elf linker functions (f9c26587f1, Alan Modra)

Top Contributors

Author	Commits
Jan Beulich	9
Mark Zhuang	3
Jiawei	3
Alan Modra	2
Jerry Zhang Jian	1

Notable Discussions

[PATCH] RISC-V: Fix build with GCC-8 14 replies — Andrew Burgess
RISC-V: Add SpacemiT vendor extension xsmtvdot 4 replies — Mark Zhuang

GDB (RISC-V)

1

Commits

1

Contributors

2

Lines Added

0

Lines Removed

GDB (RISC-V) had exactly one commit this month. This was primarily a stabilisation month — 1 of 1 commits (100%) were fixes.

1 Bug fixes

Notable Changes

[gdb] Fix codespell false positives by ignoring (5c4abfabd1, Tom de Vries)

Top Contributors

Author	Commits
Tom de Vries	1

OpenOCD (RISC-V)

7

Commits

4

Contributors

74

Lines Added

32

Lines Removed

Not the busiest month for OpenOCD (RISC-V): 7 commits from 4 contributors. Leading the charge was Antonio Borneo with 4 commits.

2 New features & support

Notable Changes

target: add poll_interval command support (3d99e54eb0, Zane Leung)
target: riscv: enable 'disassemble' command (081459d16f, Antonio Borneo)
target: riscv: error-out instead of truncating register values (25c6ac85cd, Evgeniy Naydanov)
target: aarch64: deprecate command 'aarch64 disassemble' (31b6cf090c, Antonio Borneo)
target/riscv: Mark dscratch* registers as non-cacheable (25b89a97df, Jan Matyas)
target: arm: deprecate command 'arm disassemble' (51ef16e5a2, Antonio Borneo)
target: extend use of capstone disassembler (4df157c52f, Antonio Borneo)

Top Contributors

Author	Commits
Antonio Borneo	4
Evgeniy Naydanov	1
Jan Matyas	1
Zane Leung	1

OpenBLAS (RISC-V)

1

Commits

1

Contributors

46

Lines Added

8

Lines Removed

One lone commit for OpenBLAS (RISC-V) this month.

Notable Changes

Unroll inner loop - 2 rows at a time. Up to 1.5X faster. (6a23c36313, Chip Kerchner)

Top Contributors

Author	Commits
Chip Kerchner	1

The Big Picture

RISC-V International

Spec Pipeline Changes (since May 2026)

Specification Pipeline (100 total, 51 ratified)

Ratification-Ready (3)

Freeze (15)

Stabilization (6)

Planning (15)

Inception (5)

Spec Repository Activity

Working Groups (73 total)

New Groups Being Chartered

OpenSBI

Notable Changes

Top Contributors

Notable Discussions

Mailing List Activity

QEMU (RISC-V)

Notable Changes

Top Contributors

Mailing List Activity

glibc (RISC-V)

Notable Changes

Top Contributors

Notable Discussions

Binutils (RISC-V)

Notable Changes

Top Contributors

Notable Discussions

GDB (RISC-V)

Notable Changes

Top Contributors

OpenOCD (RISC-V)

Notable Changes

Top Contributors

OpenBLAS (RISC-V)

Notable Changes

Top Contributors