RISC-V Software News

July 2026 — Upstream Open Source Activity

The Big Picture

July 2026 was on the quieter side: 100 commits across 4 projects. QEMU (RISC-V) led with 70 commits (70%). Also active: OpenBLAS (RISC-V) (15), OpenSBI (12), Eigen (RISC-V) (3). Extension support work touched Zkr. Virtualisation saw 5 KVM-related patches.

RISC-V International

RISC-V International is tracking 100 specifications, of which 51 have been ratified. Currently 20 are in the home stretch (freeze/stabilisation/ratification-ready), and 16 in planning. Specs flagged as "exposed" (at risk of slipping): Address-Independent Fault Latency (Svukte), Confidential VM Extension (CoVE), Long/Batched Dot-Product Extensions (Zvldot and Zvbdot). Keep an eye on these. Across RISC-V International, 73 working groups are tracked — 56 actively meeting, 12 running at low activity. New groups being chartered: Performance Events TG, Parameters SIG, Event Trace TG, Logic Analyzer Trace TG, Speculation Barriers TG . The spec repos saw 36 commits this month, led by ISA Manual with 32 commits.

Spec Pipeline Changes (since June 2026)

  • Data Trace of Multiple-Memory Access and Compare and Swap — Freeze → Ratification-Ready
  • Implicit Return (E-Trace 2.0) — Freeze → Ratification-Ready
  • Standard Support Packet extension to E-trace — Freeze → Ratification-Ready
  • RV Worlds H-extension — Inception → Planning

New specs entering the pipeline:

  • Dot-Product (Zvdot4a8i) (Stabilization)
  • Post-Quantum Cryptography (Keccak) (Stabilization)
  • RISC-V Indexed Integer Load (Zilx) (Planning)
  • ACLINT (Advanced Core Local Interruptor) v1.0 (Inception)
  • adsad (Inception)

Specs removed from pipeline:

  • S-mode Physical Memory Protection (SPMP) (was: Ratification-Ready)
  • Confidential VM Extension (CoVE) (was: Freeze)
  • Extra Vector Carry-Less/Crypto Extensions (Zvbc32e, Zvkgs) (was: Freeze)
  • Dot-Product (Zvqdot/Zvdot4a8i) (was: Stabilization)
  • Fast Interrupts (CLIC) (was: Stabilization)
  • Integrated Matrix Extension (IME) (was: Stabilization)
  • Vector Matrix Extension (VME) (was: Planning)

Specification Pipeline (100 total, 51 ratified)

51
Ratified
16
in Planning
10
in Freeze
6
Inception
6
Cancelled
5
Under Stabilization
5
in Ratification-Ready
1
in Publication

Ratification-Ready (5)

Freeze (10)

Stabilization (5)

Planning (16)

Inception (6)

Spec Repository Activity

RepositoryCommitsContributors
ISA Manual 32 9
ELF psABI 4 3

Working Groups (73 total)

56
Active
12
Low Activity
10
Being Chartered

New Groups Being Chartered

  • Performance Events TG — chaired by Beeman Strong (Meta)
  • Parameters SIG
  • Event Trace TG — chaired by Bruce Ableidinger (MIPS)
  • Logic Analyzer Trace TG — chaired by Sajosh Janarthanam (Tenstorrent)
  • Speculation Barriers TG — chaired by Ved Shanbhogue (Meta)
  • RVM Profile TG — chaired by Ozgur Ozkurt (Quintauris)
  • Automotive SIG — chaired by Thomas Roecker (Infineon)
  • Long Instruction TG — chaired by Stefan Wallentowitz (Individual Member)
  • JITed and Dynamic Languages SIG — chaired by Martin Maas (Google)
  • Vector Digital Signal Processing TG — chaired by Dmitry Utyansky (Synopsys)

OpenSBI

12
Commits
6
Contributors
1062
Lines Added
175
Lines Removed

A quieter month for OpenSBI, with 12 commits from 6 contributors. Pawandeep Oza was the most active contributor with 6 commits. AIA and interrupt controller work accounted for 8 patches.

8 Interrupt controllers (AIA/APLIC/PLIC) 4 New features & support 2 Bug fixes

Notable Changes

  • lib: utils/irqchip/aplic: add MSI mode support with IMSIC parent linking (759910326c, Pawandeep Oza)
  • lib: utils/irqchip/imsic: track IRQ enable state and restore EIE on warm init (and 2 more) (b2ead3b037, Pawandeep Oza)
  • lib: utils/irqchip/aplic: implement direct mode irqchip callbacks (5ee0559445, Pawandeep Oza)
  • lib: utils/mpxy: Add RPMI MPXY driver for logging service group (262571217c, Subrahmanya Lingappa)
  • lib: sbi_irqchip: fix MSI EIID gap and tail allocation logic in register_msi (7a90f41fb9, Pawandeep Oza)
  • lib: sbi_irqchip: fix device lookup by caps when first is NULL (92bea7bdb2, David E. Garcia Porras)
  • lib: sbi_ipi: Validate hartids against domain, not HSM state (110f28518a, Chen Pei)
  • lib: utils/mpxy: bind channel access to owning domain (c0f87f10d1, Oza Pawandeep)
  • lib: sbi: Move trap delegation setup to sbi_trap.c (c504877ed0, Anup Patel)
  • include: Bump-up version to 1.9 (cbf9f6734d, Anup Patel)

Top Contributors

AuthorCommits
Pawandeep Oza6
Anup Patel2
Oza Pawandeep1
Chen Pei1
David E. Garcia Porras1
Subrahmanya Lingappa1

Notable Discussions

Mailing List Activity

QEMU (RISC-V)

70
Commits
14
Contributors
1877
Lines Added
729
Lines Removed

QEMU (RISC-V) saw healthy activity with 70 commits from 14 contributors. Daniel Henrique Barboza was the driving force, authoring 48 of 70 commits (68%). AIA and interrupt controller work accounted for 11 patches. New feature work included 10 commits: "target/riscv/kvm: add extensions after v7.1-rc4 update"; "cpu: Introduce cpu_single_stepping() helper". KVM and virtualisation received 5 patches. ISA extension work spanned 4 commits, touching Zkr.

11 Interrupt controllers (AIA/APLIC/PLIC) 10 New features & support 5 KVM / Virtualisation 4 ISA extensions 3 Bug fixes 3 Cleanup & refactoring 3 Device tree / platform support 1 Vector extension (RVV)

Notable Changes

  • target/riscv/kvm: add extensions after v7.1-rc4 update (83a87a38b6, Wang Yechao)
  • target/riscv: tt-ascalon: Enable Zkr extension (569aa6280d, Nicholas Piggin)
  • hw/riscv/riscv-iommu: forbid GATE/SADE if caps.AMO_HWADD is zero (and 3 more) (6d2b9d542f, Daniel Henrique Barboza)
  • target/riscv/kvm: skip FP/Vector sync on KVM_PUT_RUNTIME_STATE (e2beafde9e, Meng Zhuo)
  • hw/riscv/atlantis: Ensure OpenSBI has a non-zero next_addr (39968a85c6, Alistair Francis)
  • hw/riscv/sifive_u: add #address-cells in PLIC FDT (5af6d1308b, Daniel Henrique Barboza)
  • target/riscv/cpu: add CPU unrealize callback (820552a92e, Daniel Henrique Barboza)
  • cpu: Introduce cpu_single_stepping() helper (0a8bc0f251, Philippe Mathieu-Daudé)
  • hw/riscv/atlantis: Add some i2c peripherals (50cbe23432, Joel Stanley)
  • hw/riscv: Add Tenstorrent Atlantis machine (7778f4b27b, Joel Stanley)
  • hw/riscv: add create_fdt_plic() helper (b3b4a424e2, Daniel Henrique Barboza)
  • target/riscv: move riscv_cpu_set_aia_ireg_rmw_cb() to riscv_imsic (and 16 more) (6dd762b415, Daniel Henrique Barboza)
  • target/riscv/cpu.c: filter TCG only bits in riscv_cpu_reset_hold() (and 2 more) (209638d448, Daniel Henrique Barboza)
  • hw/riscv/riscv-iommu.c: set ftype and iova in riscv_iommu_ctx() (and 11 more) (ce7fb32827, Daniel Henrique Barboza)
  • hw/riscv/riscv-iommu-sys.c: record fault on IOMMU-generated MSI write (58e801f74e, Daniel Henrique Barboza)

Top Contributors

AuthorCommits
Daniel Henrique Barboza48
Joel Stanley7
Nicholas Piggin3
Philippe Mathieu-Daudé2
Wang Yechao1
Zephyr Li1
Peter Maydell1
Alistair Francis1
Inochi Amaoto1
Charlie Jenkins1

Mailing List Activity

OpenBLAS (RISC-V)

15
Commits
4
Contributors
2359
Lines Added
78
Lines Removed

OpenBLAS (RISC-V) kept moving with 15 commits from 4 contributors. Most of the work came from moluopro (10 of 15 commits, 66%). New feature work included 11 commits: "Add Sifive U74"; "U74 target: build for the full JH7110 ISA (add Zba/Zbb)". RVV work continued with 10 commits touching vector-related code.

11 New features & support 10 Vector extension (RVV) 2 Bug fixes 1 ISA extensions 1 Compiler backend / code generation

Notable Changes

  • kernel/riscv64: enable RVV TRSM for ZVL256B (and 7 more) (0e163c9db2, moluopro)
  • U74 target: build for the full JH7110 ISA (add Zba/Zbb) (b8949d1663, hmeiland)
  • Add U74 target with a 4x4 register-tiled GEMM kernel (a3620c264a, hmeiland)
  • Add Sifive U74 (41aad1107a, Martin Kroeker)
  • U74 target: move the U74-specific gemm kernel to kernel/riscv64 (5d7868f487, Hugo Meiland)
  • U74 target: hand-scheduled scalar asm DGEMM micro-kernel (4999e881a5, hmeiland)
  • fix(riscv64): handle zero-stride ROTM in RVV kernel (f82cf88caa, moluopro)
  • fix(riscv64): keep signed strides in RVV ROTM (395f8b347f, moluopro)

Top Contributors

AuthorCommits
moluopro10
hmeiland3
Martin Kroeker1
Hugo Meiland1

Eigen (RISC-V)

3
Commits
2
Contributors
97
Lines Added
43
Lines Removed

Eigen (RISC-V) was quiet this month with 3 commits from 2 contributors. Rasmus Munk Larsen dominated with 2/3 commits (66%). Optimisation efforts accounted for 2 commits.

2 Performance optimisations 1 Bug fixes

Notable Changes

  • fp16/bf16: fix NumTraits::epsilon, half GPU raw-bit interop, RVV10 bf16 masks, and 16-bit normal RNG (40e7e38646, Rasmus Munk Larsen)
  • Core: keep NaN/Inf constants out of fast-math poison in packet kernels (b941180f8d, Rasmus Munk Larsen)
  • Perf: Use constexpr branching for static paths (b8ca06f310, Florian Maurin)

Top Contributors

AuthorCommits
Rasmus Munk Larsen2
Florian Maurin1