RISC-V Software News

October 2026 — Upstream Open Source Activity (In Progress)
Work in Progress — This report covers October 2026 which is still ongoing (18 days remaining). Numbers will change as more patches land. Check back after the month ends for the final tally.

The Big Picture

The RISC-V ecosystem saw 112 commits in October 2026 across 6 projects. LLVM (RISC-V) led with 84 commits (75%). Also active: Binutils (RISC-V) (15), OpenOCD (RISC-V) (6), GCC (RISC-V) (5). Extension support work touched QC_LI.

RISC-V International

RISC-V International is tracking 100 specifications, of which 54 have been ratified. Currently 12 are in the home stretch (freeze/stabilisation/ratification-ready), and 13 in planning. Specs flagged as "exposed" (at risk of slipping): Dot-Product and Batched Dot-Product Extensions (Zvdota and Zvbdota), CHERI, Input/Output Physical Memory Protection (IOPMP), Supervisor Domains Access Protection (Smmtt). Keep an eye on these. Across RISC-V International, 76 working groups are tracked — 54 actively meeting, 14 running at low activity. New groups being chartered: Performance Events TG, Parameters SIG, Serial Debug Protocol (RSDP) TG, Logic Analyzer Trace TG, Speculation Barriers TG . The spec repos saw 19 commits this month, led by ISA Manual with 17 commits.

Spec Pipeline Changes (since September 2026)

  • Vector Matrix Extension (VME) — Stabilization → Freeze
  • NAPOT Page Sizes (SvnapotNk) — Inception → Planning

New specs entering the pipeline:

  • Dot-Product and Batched Dot-Product Extensions (Zvdota and Zvbdota) (Freeze)

Specs removed from pipeline:

  • Long/Batched Dot-Product Extensions (Zvldot and Zvbdot) (was: Freeze)

Specification Pipeline (100 total, 54 ratified)

54
Ratified
13
in Planning
8
Inception
8
Cancelled
6
Under Stabilization
5
in Publication
5
in Freeze
1
in Ratification-Ready

Ratification-Ready (1)

Freeze (5)

Stabilization (6)

Planning (13)

Inception (8)

Spec Repository Activity

RepositoryCommitsContributors
ISA Manual 17 9
ELF psABI 2 1

Working Groups (76 total)

54
Active
14
Low Activity
6
Being Chartered

New Groups Being Chartered

  • Performance Events TG — chaired by Rajat Bhatia (Qualcomm)
  • Parameters SIG
  • Serial Debug Protocol (RSDP) TG — chaired by Anton Fogel (Lauterbach)
  • Logic Analyzer Trace TG — chaired by Sajosh Janarthanam (Tenstorrent)
  • Speculation Barriers TG — chaired by Ved Shanbhogue (Meta)
  • Long Instruction TG — chaired by Stefan Wallentowitz (Individual Member)

QEMU (RISC-V)

1
Commits
1
Contributors
3
Lines Added
0
Lines Removed

Just a single commit landed in QEMU (RISC-V) this month.

Notable Changes

  • linux-user/riscv: copy the executable's e_flags into core dumps (2b3088a857, Matt Turner)

Top Contributors

AuthorCommits
Matt Turner1

Notable Discussions

Mailing List Activity

GCC (RISC-V)

5
Commits
1
Contributors
135
Lines Added
129
Lines Removed

A quieter month for GCC (RISC-V), with 5 commits. Most of the work came from Jeff Law (5 of 5 commits, 100%). Bug fixes dominated: 4/5 commits (80%). A month focused on getting things right.

4 Bug fixes 1 ISA extensions

Notable Changes

  • [RISC-V] Remove obsolete, never taken to silicon xventanacondops extension (06cee27b69, Jeff Law)
  • [committed][RISC-V] Fix one more test fallout from AOP work on RISC-V (be2755d554, Jeff Law)
  • [RISC-V] Fix remaining AOP related regressions on the RISC-V port (de2ea1f8b1, Jeff Law)
  • [RISC-V] Fix pack* tests for RISC-V after any-or-plus changes (9d11ed33f5, Jeff Law)
  • [RISC-V] Fix pr58727 code quality regression on RISC-V (9613bdb192, Jeff Law)

Top Contributors

AuthorCommits
Jeff Law5

LLVM (RISC-V)

84
Commits
29
Contributors
15806
Lines Added
8418
Lines Removed

LLVM (RISC-V) saw healthy activity with 84 commits from 29 contributors. A hefty +15,806/-8,418 line diff. Craig Topper was the most active contributor with 30 commits. The compiler backend saw heavy activity with 28 commits touching code generation. New feature work included 19 commits: "[RISCV] Reassociate add (add X, (ext Y)), (ext Z) -> add (add (ext Y), (ext Z)), X (#230657)"; "[SelectionDAG] Add extension attribute on Memset libcall arg. (#229883)". ISA extension work spanned 10 commits, touching QC_LI.

28 Compiler backend / code generation 19 New features & support 13 Cleanup & refactoring 10 ISA extensions 6 Bug fixes 2 Vector extension (RVV) 2 Performance optimisations

Notable Changes

  • [SelectionDAG] Add extension attribute on Memset libcall arg. (#229883) (51aad57017, Jonas Paulsson)
  • [RISCV] Make sure ADDI isn't a frame index in RISCVMergeBaseOffsetOpt::foldLargeOffset. (#228635) (0fae4df99c, Craig Topper)
  • [SDPatternMatch] Add m_Node and m_SpecificOpc that take opcode from template argument (#228626) (f28445b345, Min-Yih Hsu)
  • [RISCV] Reassociate add (add X, (ext Y)), (ext Z) -> add (add (ext Y), (ext Z)), X (#230657) (5afa2c0cad, Luke Lau)
  • [RISC-V][MC] Reject x0 as the address/temporary register for load/store pseudos (#227512) (ce33479e64, Alexander Richardson)
  • [RISCV] Add a RISCVISD::TUPLE_CAST to represent casting one tuple to another. (#228249) (7eea74bb72, Craig Topper)
  • RISCV: Do not add a live VL def to inline asm that clobbers it (#229246) (and 2 more) (c279be8a73, Matt Arsenault)
  • [Clang][RISCV][P-ext] Add packed Q-format widening accumulate intrinsics (#228009) (152d32ee35, 陈子昂)
  • [RISCV] Fix violations of SDTCisSameAs when creating vector ISD nodes. (#228215) (d67ecfbfd4, Craig Topper)
  • [RISCV] Consider truncate semantics in performINSERT_VECTOR_ELTCombine (#228243) (58d59f460c, Alex Bradbury)
  • [MachineCombiner][NFC]Add tests for long chain FMA reassociation, NFC (#224126) (7380d5b2e4, Alexey Bataev)
  • [DAG] Add basic deinterleave/interleave(poison) -> poison combines. (#228858) (6607cce423, David Green)
  • [DAGCombiner] Add tests for zero-extended low-bits masks (NFC) (#229981) (a8914554d4, Chris Kennelly)
  • [RISCV] Remove redundant sign extensions from BEXT indices (#228398) (046f63ba94, tinfengyu)
  • [RISCV] Convert mask to scalable vector in lowerVPREDUCE. (#228219) (4146a3d0ba, Craig Topper)

Top Contributors

AuthorCommits
Craig Topper30
Matt Arsenault11
Luke Lau4
Zeyi Xu3
Fangrui Song3
Min-Yih Hsu3
Nikita Popov3
Sam Elliott2
tinfengyu2
Mikołaj Piróg2

Binutils (RISC-V)

15
Commits
7
Contributors
1321
Lines Added
127
Lines Removed

Binutils (RISC-V) saw moderate activity with 15 commits from 7 contributors. Leading the charge was Kito Cheng with 5 commits. New feature work included 7 commits: "RISC-V: Introduce TLSDESC relaxation."; "RISC-V: Add elf_link_hash_entry to relax_func args.". Performance work included 1 commit.

7 New features & support 5 ISA extensions 2 Bug fixes 1 Performance optimisations

Notable Changes

  • RISC-V: Add supervisor architecture support (6963071aac, Jerry Zhang Jian)
  • RISC-V: Added DT_RELR support (b0c84e4cd5, Nelson Chu)
  • RISC-V: PR30237, don't add PT_RISCV_ATTRIBUTES in objcopy/strip (97e4144904, Sungjoon Moon)
  • RISC-V: Introduce TLSDESC relaxation. (and 3 more) (2c4ccb8103, Tatsuyuki Ishi)
  • RISC-V: Add Zcmt table-jump relocation definitions (4b013df182, Jiawei)
  • RISC-V: Suppress may be used uninitialized warning (and 4 more) (079dc6f508, Kito Cheng)
  • RISC-V: Fix h->got union phase confusion for DT_RELR (e522ebecf7, Jens Remus)
  • RISC-V: Decode Zcmt JVT entries in objdump (7310b8560e, Jiawei)

Top Contributors

AuthorCommits
Kito Cheng5
Tatsuyuki Ishi4
Jiawei2
Jens Remus1
Jerry Zhang Jian1
Sungjoon Moon1
Nelson Chu1

Notable Discussions

OpenOCD (RISC-V)

6
Commits
5
Contributors
96
Lines Added
24
Lines Removed

A quieter month for OpenOCD (RISC-V), with 6 commits from 5 contributors.

3 Bug fixes 2 New features & support

Notable Changes

  • target/riscv: Rework 'set_mem_access' command (0a0dc39699, Marc Schink)
  • ipdbg: add commands to list hubs and services (12122ff80e, Daniel Anselmi)
  • flash/nor, tcl/target: add PAC55XX (fbc480aa16, stfnbr)
  • target/riscv: fix trigger bookkeeping limit (85193e2805, Matthew Waltz)
  • doc: Fix virtex2 'pld load' example usage (046dbd9790, Marc Schink)
  • doc: fix command syntax in example (6bacfd24cd, Antonio Borneo)

Top Contributors

AuthorCommits
Marc Schink2
Antonio Borneo1
Daniel Anselmi1
Matthew Waltz1
stfnbr1

Eigen (RISC-V)

1
Commits
1
Contributors
14
Lines Added
1
Lines Removed

Just a single commit landed in Eigen (RISC-V) this month. RVV work continued with 1 commit touching vector-related code.

1 Vector extension (RVV) 1 New features & support

Notable Changes

  • RVV: Enable generic packet sinh, cosh, asinh, acosh, atan, atanh, log10, log1p, expm1, pow, cbrt, rsqrt and erfc (630f81dbf0, Chip Kerchner)

Top Contributors

AuthorCommits
Chip Kerchner1